Experience

Hindustan College of Science & Technology

• Professional Training and Coaching
• 1 - 100 Employee

• Head Of Department

  • Jan 2001 - Present

  Professor & Head of Dept of Electronics & Communication Engineering, supervising faculty and staff and teaching. Professor & Head of Dept of Electronics & Communication Engineering, supervising faculty and staff and teaching.



RBS College, Agra

• India
• Higher Education
• 1 - 100 Employee

• Head Of Department

  • Sep 1998 - Dec 2000

  As Reader & Head, Dept. of Electronics & Communication Engineering, developed curriculum and laboratories in addition to administration and teaching. As Reader & Head, Dept. of Electronics & Communication Engineering, developed curriculum and laboratories in addition to administration and teaching.



Sarnoff Corporation

• Research Services
• 1 - 100 Employee

• Technical Team Member

  • Oct 1997 - Aug 1998

  As Member of Technical Staff, performed integration and development of CMOS CCD processes with multiple levels of poly-Si and metal. Engineered innovative process modules for buried contacts and active area gate contacts/straps. Designed test chip for CCD process. Developed MEMS release process sequence of resist strip, wet oxide etch and high pressure supercritical CO2 drying for release of delicate cantilever type MEMS structures. Achieved stiction free release of strands 0.2um thick and 400um long. Show less



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Device Engineer

  • Oct 1996 - Sep 1997

  As Sr Device Engineer, performed electrical characterization of flash memory cell and diagnostic test structures in 0.35um process on benchtop and automatic wafer prober. Work included measurement, analysis, programming in hpbasic, and use of RS/1. Also developed and documented new test structures for advanced processes. As Sr Device Engineer, performed electrical characterization of flash memory cell and diagnostic test structures in 0.35um process on benchtop and automatic wafer prober. Work included measurement, analysis, programming in hpbasic, and use of RS/1. Also developed and documented new test structures for advanced processes.



Office of Research University of California Santa Barbara

• United States
• Higher Education
• 1 - 100 Employee

• Researcher

  • Jun 1995 - Sep 1996

  As Researcher, worked on GaN based power devices. Performed DLTS characterization of insulator - GaAs interface. As Researcher, worked on GaN based power devices. Performed DLTS characterization of insulator - GaAs interface.



Semtech

• United States
• Technology, Information and Internet
• 700 & Above Employee

• R&D Manager

  • Feb 1990 - May 1995

  As R&D Manager, designed switching power supplies 100W to 10 KW. Developed new methods for design of ferrite transformers and inductors. As R&D Manager, designed switching power supplies 100W to 10 KW. Developed new methods for design of ferrite transformers and inductors.



Indian Institute of Technology, Kanpur

• India
• Higher Education
• 700 & Above Employee

• Assistant Professor

  • Mar 1989 - Feb 1990

  As Assistant Professor in Dept of Electrical Engineering, taught and developed laboratory for semiconductor research. As Assistant Professor in Dept of Electrical Engineering, taught and developed laboratory for semiconductor research.



Bell Laboratories, Inc.

• United States
• Manufacturing
• 1 - 100 Employee

• Technical Team Member

  • Jul 1985 - Feb 1989

  As Member of Technical Staff, worked in areas of silicon wafer processing, process integration, device characterization, simulation and design of test structures. Developed new sloped junction LDD MOSFET structures with reduced hot-carrier effects. Developed advanced two-level metal process technologies for 0.6, 0.8, 1.25 and 1.5um twin-tub CMOS processes. Dielectric planarization by etchback and SOG methods were implemented. Contact plug deposition by selective and blanket tungsten and electroless plating was studied. Developed experimental four level metal CMOS process and related test chip. Performed simulation using BICEPS process simulator and MINIMOS device simulator in Unix environment. Performed computer-aided parametric testing of devices using IEEE488 instrument interface. Developed new methods for MOSFET characterization. Show less



Lehigh University

• United States
• Higher Education
• 700 & Above Employee

• Master Thesis

  • Aug 1980 - Jun 1985

  (Thesis Work) Fabricated MOS structures with ultra-thin 20 – 43 A oxide and studied trapping and tunneling phenomenon in interface charge transients. (Thesis Work) Fabricated MOS structures with ultra-thin 20 – 43 A oxide and studied trapping and tunneling phenomenon in interface charge transients.