Divya Jamakhandi

Graduate Teaching Assistant at College of Natural Sciences, The University of Texas at Austin
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Contact Information
us****@****om
(386) 825-5501
Location
Austin, Texas, United States, US

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Experience

    • United States
    • Higher Education
    • 100 - 200 Employee
    • Graduate Teaching Assistant
      • Aug 2023 - Present

      Department of Astronomy Department of Astronomy

    • United States
    • Computers and Electronics Manufacturing
    • 700 & Above Employee
    • GPU RTL Design Intern
      • May 2023 - Aug 2023

      Worked on RTL design for various features for the Front End units of the Shader Core while meeting power, performance and area targets. Worked on various design flows such as sequential equivalence checks, X-propagation checks and timing analysis. Worked on RTL design for various features for the Front End units of the Shader Core while meeting power, performance and area targets. Worked on various design flows such as sequential equivalence checks, X-propagation checks and timing analysis.

    • United States
    • Higher Education
    • 100 - 200 Employee
    • Graduate Teaching Assistant
      • Jan 2023 - May 2023

      Department of Mathematics Department of Mathematics

    • United States
    • Telecommunications
    • 700 & Above Employee
    • Engineer
      • Nov 2021 - Jul 2022

      SMMU IP RTL Design Engineer• Developed Micro Architecture and RTL from scratch for MMU blocks like Walker, Cache and interface protocols and delivered to Qualcomm SOCs across various tiers ranging from IoT to premium mobile applications.

    • Associate Engineer
      • Jun 2020 - Nov 2021

      SMMU IP RTL Design Engineer• Designed Power and Clock controllers to reduce the IP Leakage Power and support a Power Collapsible SMMU Island.• Worked on various post design RTL flows like Lint, CDC, STA and SOC debugs and efficiently handled multiple crucial ECOs by performing netlist modifications to implement equivalent RTL Logic for late bugs.

    • Engineering Intern
      • Jan 2020 - Jun 2020

      Designed micro-architecture and RTL for multiple PPA enhancement features on the base SMMU IP.

    • India
    • Research
    • 700 & Above Employee
    • Summer Research Intern
      • Jun 2019 - Aug 2019

      Implemented resource efficient 2D-Discrete Cosine Transform for feature extraction as a hardware accelerator and performed multiple layers of DCT aimed at extraction of features from Video frames on Zynq Ultrascale Board. Implemented resource efficient 2D-Discrete Cosine Transform for feature extraction as a hardware accelerator and performed multiple layers of DCT aimed at extraction of features from Video frames on Zynq Ultrascale Board.

    • India
    • Biotechnology Research
    • Embedded IOT Intern
      • Jun 2018 - Aug 2018

      Developed a Wheel Chair Monitoring system and worked on interfacing 3-Axis accelerometer and gyroscope with Arduino Development Board. Interfaced GSM Module, Real Time Clocks and External EEPROMS with the System. Developed a Wheel Chair Monitoring system and worked on interfacing 3-Axis accelerometer and gyroscope with Arduino Development Board. Interfaced GSM Module, Real Time Clocks and External EEPROMS with the System.

    • India
    • Aviation and Aerospace Component Manufacturing
    • 1 - 100 Employee
    • Subsystem Engineer
      • Sep 2016 - Dec 2017

      Engineer at Electronics and Control Logic subsystem and Payload Subsystem at the young nano satellite building team. Engineer at Electronics and Control Logic subsystem and Payload Subsystem at the young nano satellite building team.

Education

  • The University of Texas at Austin
    Master of Science - MS, Electrical and Computer Engineering
    2022 - 2024
  • R. V. College of Engineering, Bangalore
    Bachelor of Engineering, Electronics and communication
    2016 - 2020
  • K.L.E Society S. Nijalingappa College, Rajajinagar, Bangalore-10
    Pre University, Science stream - Electronics elective
    2014 - 2016
  • Venkat International Public School
    High School (CBSE), 10 CGPA
    2011 - 2014

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