Experience

RFMD (now Qorvo, Inc.)

• United States
• Semiconductor Manufacturing
• 400 - 500 Employee

• Staff Layout Engineer

  • Feb 2014 - Present

  Switch and switch controllers Switch and switch controllers



Andrews Consultant Service

• Greensboro/Winston-Salem, North Carolina Area

• Staff MMIC Engineer/IC Layout Engineer

  • Sep 2012 - Present

  Contract transceiver layout engineer - multiple processes, multiple CAD platforms RF/MMIC Designer/Layout - GaAs RF/Microwave characterization testing Contract transceiver layout engineer - multiple processes, multiple CAD platforms RF/MMIC Designer/Layout - GaAs RF/Microwave characterization testing



OrthoRadio Corp

• Greensboro/Winston-Salem, North Carolina Area

• Sr Layout Engineer

  • Oct 2010 - Aug 2012

  Chip Layout Lead Engineer for transceiver chips - floor planning of entire transceiver, managing layout resources, verification of chip, layout of major modules, critical matching, critical power matching, pex of layout, etc. RX/RF characterization testing of transceiver chips - modification of test program as required, development of controlling spreadsheets, development of data analysis spreadsheets. Chip Layout Lead Engineer for transceiver chips - floor planning of entire transceiver, managing layout resources, verification of chip, layout of major modules, critical matching, critical power matching, pex of layout, etc. RX/RF characterization testing of transceiver chips - modification of test program as required, development of controlling spreadsheets, development of data analysis spreadsheets.



Huawei

• China
• Telecommunications
• 700 & Above Employee

• Contract Senior Layout Engineer

  • Jun 2010 - Sep 2010

  Contract Senior Layout Engineer for RF portion of transceiver chip at Huawei in Louisville, CO. Work includes floor planning, layout, critical matching, critical power routing. Contract Senior Layout Engineer for RF portion of transceiver chip at Huawei in Louisville, CO. Work includes floor planning, layout, critical matching, critical power routing.



Andrews Consultant Services

• Greensboro/Winston-Salem, North Carolina Area

• Staff IC Layout Engineer

  • Oct 2009 - Apr 2010

  Contract Senior Layout Engineer at OrthoRadio for the fraction n PLL for Titan chip. All work includes floor planning of major blocks, layout of modules, critical matching/critical power routing, top chip routing. Contract Senior Layout Engineer at OrthoRadio for the fraction n PLL for Titan chip. All work includes floor planning of major blocks, layout of modules, critical matching/critical power routing, top chip routing.



Andrew Consultant Services, LLC

• Colorado Springs, Colorado Area

• Staff IC Layout Engineer

  • Jun 2008 - Jun 2009

  Contract Senior Mask designer for ON Semiconductor in the Medical Division. Processes used TSMC RF/HV and ON/AMIS using design for manufacture techniques besides strict medical layout techniques. Floor planning and layout of four ASICs: one ASIC for medical test trials in hypertension and three ASICs used in medical equipment for ECG, blood pressure, and glucose testing. All four ASIC were first pass successes. Mentor to several junior engineers for proper design to layout techniques. Project layout lead with responsibilities including pad frame design, major layout blocks floorplanning, supervision of other layout contractors, layout of major blocks including IP, working with CAD for corrections to Caliber rule decks, and running of parasitic extractions for all major layout blocks for engineering simulations.



Additional Contract Services - National Division

• United States
• Staffing and Recruiting
• 1 - 100 Employee

• Senior IC Mask Designer

  • 2007 - 2008

  Contract Senior Mask designer at RFMD for the oscillator in the Lodestar chip using TSMC90NLP CMOS process involving critical matching for noise and phase and for the Deuce Power Monitor mixed signal chip using IBM CMOS7RF CMOS process involving critical matching for power plus analog matching, using place and route for digital high speed, and floor planning. Contract Senior Mask designer at RFMD for the oscillator in the Lodestar chip using TSMC90NLP CMOS process involving critical matching for noise and phase and for the Deuce Power Monitor mixed signal chip using IBM CMOS7RF CMOS process involving critical matching for power plus analog matching, using place and route for digital high speed, and floor planning.



Atmel

• Senior Principal Mask Engineer

  • 2000 - 2006

  Created K2 data prep mask flow for each new process to build frames/reticles including paperwork generation for mask vendor resulting in error free masks. Created mask flows for projects that utilized multiple dice with unique sizes; this auto placement eliminated tedious hand corrections and resulted in faster error free tapeouts. Verified MEBES data from mask vendor for initial creation of new tapeout procedures/processes resulting in zero defects in mask. I was frequently called upon to transfer and improve tapeout procedures from outside fabs to the local Atmel fab due to my high success rate and fewest errors. Created DRC and sizing rules including OPC in CMOS gates. Developed process control modules for etest data of each technologies and created process specific framing data for fab optical measurements Built mask/die prep department: bootstrap-trained and supervised mask technician in addition to the above responsibilities. Received high praise for this accomplishment from upper management Developed CMOS/BiCMOS technology files and libraries for over five processes including the layout of FETs, CMOS, capacitors, resistors, varactors, and ESD diodes from process developer notes and preliminary design rule manuals. This included the development of test chips for modeling and test circuits such as LNAs, oscillators, D/A converters.. Created procedure to take customer data from stream in, DRC, log checking and conversion to mask data. Reduced time required for this procedure from over two days to less than 8 hours. This resulted in zero errors in tapeout. Often back-engineered customer layouts into schematics for purposes of troubleshooting in concert with Yield, Failure Analysis, and Product engineering resulting in recognition from division Vice President. Developed backup procedure to store mask/customer data for easy retrieval by Yield and Product Engineering.



Boeing

• United States
• Aviation & Aerospace
• 700 & Above Employee

• Microwave Senior Design Engineer

  • 1984 - 2000

  Designed 20Ghz modulator/demodulator for proof-of-concept, several stripline antenna feed network used in radar calibration project. Design microstrip switching matrix for 300W transceiver Propagation studies for 16 QAM 450 MHX transceiver Link budget analysis of point-to-multipoint system Technical assistance to marketing Layout/floorplanning of mixed signal ASICS Rad hard design of semiconductors LNA and phase shifter design and layout for phased array antenna using GaAS and InP Phemt CAD Tool Manager - including writing drc/lvs rules and incorporation of process specify device libraries RF/MMIC test engineer Evaluation of CAD packages



TRW/EPI

• IUS Project Senior Engineer

  • 1983 - 1984

  Project engineer for Inertial Upper Stage S-Band transponder used in the launching of satellites from the Space Shuttle. Improved transponder quality and reliability by upgrading test procedures and testing equipment, interfacing with design and manufacturing engineering to incorporate higher-quality components, and critical analysis of assembly techniques and subsequent implementation of corrective actions. Project engineer for Inertial Upper Stage S-Band transponder used in the launching of satellites from the Space Shuttle. Improved transponder quality and reliability by upgrading test procedures and testing equipment, interfacing with design and manufacturing engineering to incorporate higher-quality components, and critical analysis of assembly techniques and subsequent implementation of corrective actions.



Motorola Government Equipment Group

• Senior Engineer

  • 1981 - 1983

  Analysis and characterization of noise figure/associated gain of Gaas Fets for LNA used in outer space Analysis and characterization of noise figure/associated gain of Gaas Fets for LNA used in outer space



Texas Instruments

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Product engineer

  • 1978 - 1981

  Product engineer on HARM Receiver - test/layout/fabrication/inspection of stripline PCB modules, authored test procedures, assembly instructions, calibration procedures. Product engineer on HARM Receiver - test/layout/fabrication/inspection of stripline PCB modules, authored test procedures, assembly instructions, calibration procedures.