Experience

Dali Wireless

• United States
• Telecommunications
• 1 - 100 Employee

• Senior FPGA Developer

  • Nov 2016 - Present

  All aspects of CPRI payload data manipulation and routing DSP algorithm development, modeling and implementation Board level system bring-up and debug All aspects of CPRI payload data manipulation and routing DSP algorithm development, modeling and implementation Board level system bring-up and debug



Dali Wireless

• United States
• Telecommunications
• 1 - 100 Employee

• Senior FPGA Developer

  • Jan 2015 - May 2016

  Introduced an FPGA design flow which included: -introduction of a revision control system -scripted automated build system -AXI-LITE IP infrastructure for the modular definition of system control planes (configuration and status registers) Implemented standards compliant CPRI PHY layer block using the Xilinx GTX transceivers. The block is fully software configurable and can be configured to operate from CPRI line rates 1 to 8 through its register interface. Introduced an FPGA design flow which included: -introduction of a revision control system -scripted automated build system -AXI-LITE IP infrastructure for the modular definition of system control planes (configuration and status registers) Implemented standards compliant CPRI PHY layer block using the Xilinx GTX transceivers. The block is fully software configurable and can be configured to operate from CPRI line rates 1 to 8 through its register interface.



Teradici Corporation

• Engineering Manager - Silicon Validation

  • Apr 2005 - Jan 2015

  Amongst the first employees at Teradici, I was primarily responsible for the FPGA prototyping, bring up, and validation of Teradici’s PCoIP SOC ASIC devices. During the early days as the company was growing I was also directly involved with customers and sales support, performing, applications and sales engineering and directly assisting with customer issue resolution. As the company grew further, I helped build up both the validation and applications engineering teams. Amongst the first employees at Teradici, I was primarily responsible for the FPGA prototyping, bring up, and validation of Teradici’s PCoIP SOC ASIC devices. During the early days as the company was growing I was also directly involved with customers and sales support, performing, applications and sales engineering and directly assisting with customer issue resolution. As the company grew further, I helped build up both the validation and applications engineering teams.



PMC-Sierra is now Microsemi

• Semiconductor Manufacturing
• 300 - 400 Employee

• System Design and Validation Engineer

  • 1999 - 2005

  Responsible for the validation of prototype telecommunication ASICS. These are complex multi-million gate devices which implement complete PHY layer SONET and/or PDH functionality and have in excess of 1000 configuration registers. Protocols include SONET, PDH, ATM, and POS. Bus protocols include UTOPIA/POS levels 2&3, SBI and other proprietary signaling protocols. Validation includes many diverse stages all of which I have been directly responsible for on numerous projects: -Formulation of a Test Plans -Development of Hardware Test Platforms -FPGA Design and Coding -Software Test Environments -Execution of Feature Tests Show less