Experience

ZeroPoint Technologies
• Wellness and Fitness Services
• 1 - 100 Employee
• Computer Architecture Consultant

  • Oct 2022 - Present


Nokia

• Finland
• Telecommunications
• 700 & Above Employee

• SoC Design Engineer

  • Jul 2021 - Aug 2022

  - Performed design, verification and implementation tasks. - Studied the viability of technical solutions (R&D). - Contributed and participated to SoC and LTE/5G system architecture development. - Created IP biocks and subsystems to ASICs and FPGAs with latest technology. - Cooperated with others to solve technical issues. - Restructured, tested, searched for bugs, debugged and fixed existing code to make it comply with SE practices. - Performed design, verification and implementation tasks. - Studied the viability of technical solutions (R&D). - Contributed and participated to SoC and LTE/5G system architecture development. - Created IP biocks and subsystems to ASICs and FPGAs with latest technology. - Cooperated with others to solve technical issues. - Restructured, tested, searched for bugs, debugged and fixed existing code to make it comply with SE practices.



Inria

• France
• Research Services
• 700 & Above Employee

• Research Assistant

  • Oct 2017 - Dec 2020

  Memory Systems & Memory Compression Research on design, simulation and evaluation of cache and memory compression to increase their feasibility in real hardware: • Implementation and analysis of state-of-the-art hardware compression techniques • Analysis of cache and memory in a multi-level-compression environment • Development of a novel cache compression method • Daily use of C++, Python, gem5 and Git. Seldom use of Verilog for area verification. Memory Systems & Memory Compression Research on design, simulation and evaluation of cache and memory compression to increase their feasibility in real hardware: • Implementation and analysis of state-of-the-art hardware compression techniques • Analysis of cache and memory in a multi-level-compression environment • Development of a novel cache compression method • Daily use of C++, Python, gem5 and Git. Seldom use of Verilog for area verification.



Universidade Estadual de Campinas

• Brazil
• Research Services
• 700 & Above Employee

• Research Assistant

  • Aug 2015 - Jul 2017

  Caches & Cache Compression• Analysis, simulation and evaluation of the effectiveness of existing cache compression techniques• Implementation (C++ and Verilog) of state-of-the-art hardware compression methods• Proposal of extensions to a state-of-the-art cache compression scheme

• Instructor Teaching Assistant

  • Aug 2016 - Dec 2016

  Teaching assistant of a data structures undergraduate course.



LSI-TEC

• Brazil
• Research Services
• 1 - 100 Employee

• ASIC Design Engineer

  • Jan 2015 - Mar 2015

  Implementation of low-level modules for an FPGA project • Standardization and testing of existing code • Development of a PWM module in Verilog • Development of SPI, UART and PWM modules in C Implementation of low-level modules for an FPGA project • Standardization and testing of existing code • Development of a PWM module in Verilog • Development of SPI, UART and PWM modules in C



CNPq

• Brazil
• Education Administration Programs
• 700 & Above Employee

• Research Assistant

  • Aug 2011 - Aug 2012

  GPU Shaders Research in shadows development for virtual games: • Implementation and comparison of shadow-rendering algorithms using OpenGL, C++ and Python GPU Shaders Research in shadows development for virtual games: • Implementation and comparison of shadow-rendering algorithms using OpenGL, C++ and Python