Experience

Avnet ASIC Israel

• Israel
• Appliances, Electrical, and Electronics Manufacturing
• 1 - 100 Employee

• DFT/Backend Engineer

  • Oct 2020 - Present

  • Floor-plan , Place&Route ,Timing Closure & debug, STA, Clock Tree Synthesis, Power Grid Analysis and LVS/DRC debug. • Working with SYNOPSYS CAD for ASIC design (DC, ICC/ICC2, Fusion and Prime Time). • Reasonable for all blocks and FC IR drop ,power EM and signal EM values. Creating the power grid and calculating static and dynamic results using Redhawk and RHSC. • Full Chip Integration. • MBIST generation and insertion for FC and block level flow using Tessent, Mentor tool or SMS/YA Synopsys tool. • Scan and ATPG implementation on several complex chips. • Good Familiarity with RTL to GDS flow. • Basic Knowledge in Logic Design. Show less



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Backend and Physical Design Engineer

  • Nov 2019 - Oct 2020

  Develop part of intel's chips including logic scheme, place, route and optimization.

• Physical Design Engineer

  • Nov 2018 - Nov 2019

  HW Engineering and Board design at PTK R&D center.The work includes Package and PCB Layout design.