Daniel Ferrão
Digital IC Designer at Chipus Microelectronics- Claim this Profile
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Bio
Experience
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Chipus Microelectronics
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Brazil
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Semiconductors
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1 - 100 Employee
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Digital IC Designer
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Apr 2014 - Present
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Physical IC Designer
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May 2008 - Mar 2014
Digital layout Implementation, Top level integration, Logic Synthesis, LEC, Place & Route, Clock syntehsis, STA, SI Analysis, Physical Verification (DRC/LVS, Antenna), Power Analysis, Timing constraints analysis and verification. Digital layout Implementation, Top level integration, Logic Synthesis, LEC, Place & Route, Clock syntehsis, STA, SI Analysis, Physical Verification (DRC/LVS, Antenna), Power Analysis, Timing constraints analysis and verification.
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Internship at clock design project
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Sep 2006 - Mar 2008
Physical IC layout - Floorplanning, Place & Route, Cell Characterization, Clock Tree Synthesis, Timing Closure, Crosstalk and Noise Analysis, Physical Verification. Physical IC layout - Floorplanning, Place & Route, Cell Characterization, Clock Tree Synthesis, Timing Closure, Crosstalk and Noise Analysis, Physical Verification.
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IC Designer
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May 2005 - Sep 2006
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Education
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2003 - 2005
Federal University of Rio Grande do Sul
Master, Computer Science -
1999 - 2003
Universidade Federal de Pelotas
BS, Computer Science - EDA for Timing Analysis
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