Experience

4ASICs

• Malaysia
• Design
• 1 - 100 Employee

• VP & CTO

  • Jan 2017 - Present

  Founded 4ASICs Penang, Malaysia and Denmark with Michael Deruginsky (https://www.linkedin.com/in/michaelderuginsky/) in 2016/2017. We offer Custom/Analog Layout services to customer range from block level layout to full chip assembly (analog mixed mode and/or RF + ‘smaller’ digital control blocks through 3rd party strategic partners). Besides, we also provide layout management (working as lead layout with customer contract resources and add 4ASICs resources) Specialize: ….in Physical Layout Design of Size Constrained, Low-Noise, Low-Leakage, Low-Power, High PSRR & Extremely High-Impedance (>TΩ) Analog, Mixed Signal & RF Designs ….in High Volumes (100+Mpcs annually) ....in various foundries Technology from 0.35µm down to 16nm ….using Cadence, Synopsys & Mentor EDA Show less



Knowles Corporation

• United States
• Appliances, Electrical, and Electronics Manufacturing
• 700 & Above Employee

• ASIC Layout Design Engineer - Staff Engineer ll

  • Aug 2013 - Dec 2016

  Worked in microphone project with 0.35um process node. Owned 2 of the most critical blocks which are Amplifier and Charge Pump as well as the top level of the microphone full chip in 2013. Moved to support Denmark counterpart in project which on 0.18um process node, owned oscillator layout design and support high resistor and metal changed layout for most of the layout in the project. After that, switch to work on local own 0.18um process node project. In this project, I am working on the full chip level which involves die size estimation and floor planning. I also owning blocks such as the High Voltage Charge Pump , Precharge Pump, Amplifier, oscillator, RF filter and output filter, ESD and some other non-critical blocks. Show less



Altera

• United States
• Semiconductors
• 700 & Above Employee

• Layout Engineer - Member of Technical Staff (MTS)

  • Jul 2010 - Aug 2013

  - Worked in IO team as DDRIO specialist and currently working in IO team and lead the 20nm project; work with multiple cross functional team such as design, PnR and full chip integration team on aligning the milestone schedule as well as delivery. I also lead and work on the ESD layout cells in Penang on 20nm family projects. - Worked in Analog team on 28nm project and owned Receiver (RX) block and worked on Top IP integration including the bump route for total of 96 bumps. After that, I moved to another 28nm project and owned and worked on the iCDR(Clock & Data Recovery) functional block. Then continue to work in analog team on the 28nm TestChip and owned the transmitter (TX) block. I was working together with US DE to finalize the TX floor plan and work out the schedule. Last project which worked on analog layout was the 20nm Test Chip (end of 2011- mid 2012 time frame). Owned and lead the transmitter (TX) functional block. - Beside layout activities, I also actively participate and contribute on the Layout Methodology (for 20nm and 28nm process) definition and enable productivity improvement and capability development. Also lead 2 Working Group (WG) which are Density WG and Metal grid WG. - On technical paper contribution, I submitted 2 papers for Altera Technical Symposium (ATS) in 2011 which are “Patterned Layout Construction for In Context Density” and “Pre-RCE (Resistance Capacitance Extraction) Model Circuit And Smart Virtual Route Simulator”. For 2012 ATS, I also submitted 2 papers which are “Gridded Routing Methodology In Achieving Correct By Construction On Mask Design” and “Smart-Partition Tactic In Achieving Fast Turn around Time For Full Chip Dummification”. And for 2013, I have submitted the abstract for ATS 2013. The title of the paper as “Virtual Density Ring Mechanism As Early Detection In IP Prior To Integration Assembly”, this paper has been continue by my co-author and then has been selected as merit paper in ATS 2013 after I left. Show less



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Mask Design Engineer

  • Dec 2001 - Jul 2010

  - Worked in most of the CPU projects which Penang Design Center involved within 2001 to 2010. Projects involved such as Nortwood, Tejas, Prescott, Cedar Mill, Whitefield, Nehalem, Westmere and etc. which up to 22nm process. For 22nm process project, worked and co-led the DDR team with another colleague where we oversee the overall progress of DDR fubs. I was the owner and coordinator for all DDR fub activities to ensure DDR fubs are able to progress as planed and delivered with high quality layout. I am also the key contact person between Penang and US on any DDR related issue and progress. Also worked on analog IP; Transmitter (TX). In previous projects, layout which worked on included DDR, Analog IP, Clock Distribution, SDP and RF fubs. Led Clock Distribution layout team in Penang and report directly to Bangalore Design Center (BDC) India. Besides, I was the expert user lead on DFM for Penang CPU Layout team. - On technical paper, I contributed a paper (Mixed-Signal VLSI Layout Design Automation Tool for Transition Region Generation) to external technical conference (ICCAIE 2010) as main author. And this paper has been presented by my counterpart and been published at IEEE explorer (http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=5735038&queryText%3DMixed-Signal+VLSI+Design+Automation%26openedRefinements%3D*%26searchField%3DSearch+All). - Also worked with DA on developing the automation and productivity improvement flows to counter the long run time on DFM tool and also the limitation on typical auto route tool (not able to run at sub block or lower level). These 2 developments has been filed as technical paper in IMTS and DTTC in 2009 as “Smart Divide and Conquer Method For Achieving High Speed DFM Insertion Tool” (merit paper in IMTS) and “, Block Level Auto Route”. Show less