Experience

Ethernovia

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• GM and Senior Director of Engineering

  • févr. 2020 - - aujourd’hui



Peraso Inc.

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Senior Director of Digital Design

  • mai 2017 - févr. 2020

• Director of Digital Design

  • oct. 2013 - févr. 2020

  Responsible for digital ASIC development including specification, architecture, design, verification, COT physical implementation, FPGA prototyping, validation and methodologyProducts include 802.11ad baseband processors and 802.11ad radios



ASICFactory Inc.

• Owner

  • juil. 2011 - oct. 2013

  I founded ASICFactory with the objective to provide high quality and low cost services to customers for a wide range of their difficult IC development tasks.My experience in Architectural Development, Methodology Development, RTL Development, DFT, Synthesis, Low Power Development, Low Power Analysis, Place and Route, Physical Verification and STA allow me to take on a wide variety of technical and leadership roles.Customer engagementSuccessfully developed a 802.11ad baseband processor including development of complete ASIC flow Operated as a hands-on chip architect and project leadSet up a complete highly automated ASIC flow, including verification with hardware/software co-verification of a multi-CPU SOC using Synopsys ARC processors, COT hierarchical physical low, STA flow, Synthesis flows supporting DC and RC, Logical Equivalence flows, Lint and CDC checking with Spyglass, Core Assembler AHB/APB peripheral construction flow. Architected a 802.11ad verification platform which supported random constrained packet generation with checking for all levels of development including standalone block development through to chip level and validation support.Architected an FPGA development platform which enabled early software development and hardware verification of the baseband processor MAC configured in a fully functioning cross-connect configuration which supported bidirectional link traffic and facilitated host driver development. Successfully developed 2 generations of digital interface of 802.11ad radios including automated generation of hierarchical configuration register RTL interfacing to SPI and associated verification/validation stimulus, with html and rtf documentation support, and various software support deliverablesSupervised a team consisting mainly of sub-contractors and a handful for full-time employees to provide a cost effective development program



Fresco Microchip

• Director of Product Development

  • janv. 2006 - juil. 2011

  Responsible for ASIC Development and Chip Assembly.Provided project management leadership on all of the Fresco's Demodulator IC'sLead the digital IC development teamImproved and streamlined digital IC flowsIntroduced rigorous review and signoff processLead the architectural development of digital portion of IC'sCo-architected the Mixed Signal interfaces

• Manager Chip Assembly

  • janv. 2006 - avr. 2010

  Provided project management leadership on all of the Fresco's Demodulator IC'sLead the digital IC development teamDeveloped highly automated flow for RTL2GDS including foundry interface. Designed the digital DFT strategy for all Fresco's IC's and worked closely with Operations to get parts successfully into multi-million volumes with very low digital test cost.Developed a highly automated and accurate power flow using frontend low cost tool suiteArchitected the unit test veriification flow which helped allign the DSP teams models and the ASIC teams code Negotiated CAD and services contracts



Silicon Optix

• Semiconductors
• 1 - 100 Employee

• Chip Assembly Manager

  • sept. 2003 - déc. 2005

  Responsible for introduction of COT and managed P&R, DFT, STA, LEC and IP acquistion. Responsible for introduction of COT and managed P&R, DFT, STA, LEC and IP acquistion.



Cogency Technology

• Engineering Manager, Director of CAD

  • 1995 - 2003



The University of Manchester

• United Kingdom
• Higher Education
• 700 & Above Employee

• Research Fellow

  • août 1992 - août 1995

  Research into deployment of self-timed logic in consumer products in collaboration with Philips Research Labs in Einhoven. Involved comparison of self-timed and synchronous design methodology and development of support CAD methodology. Research into deployment of self-timed logic in consumer products in collaboration with Philips Research Labs in Einhoven. Involved comparison of self-timed and synchronous design methodology and development of support CAD methodology.



British Manufacture and Reseach Company

• Electrical and Electronic Apprentice

  • août 1985 - juin 1989

  Various roles, ended in electronic design Various roles, ended in electronic design