Christopher Madden

Senior Principal Engineer at Ayar Labs
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Contact Information
us****@****om
(386) 825-5501
Location
San Francisco Bay Area, US

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Experience

    • United States
    • Computer Hardware Manufacturing
    • 1 - 100 Employee
    • Senior Principal Engineer
      • 2020 - Present

    • United States
    • Semiconductors
    • 500 - 600 Employee
    • Engineering Director
      • 2018 - 2019

      IP Cores DivisionSignal Integrity Test and Analysis Lead on PAM-4 CEI-56G/112G-LR (400GAUI-8-LR/400GBASE-KR4) SERDES products.

    • Technical Director
      • 2016 - 2018

      Rambus LabsSERDES Tx/Rx AFE design and test for Cryogenic-memory front-side bus. Transferred AFE design and socket concept to customer for interface to superconducting processor. Signal Integrity and Power Integrity Lead on memory-controller testchip.

    • Senior Principal Engineer
      • 2008 - 2016

      Memory and Interfaces DivisionSignal Integrity Test Lead for Terabit Bandwidth Initiative (16-20Gb/s/pin memory PHY) and Rambus Mobile Memory Initiative (stacked die, 4x faster than LPDDR2 and 3 years before LPDDR3). Timing-jitter and proprietary-memory-system voltage-timing budgeting expert. Signal Integrity Lead on 10GBASE-KR / PCIe3 SERDES product, 100GBASE-KR4 / CEI-28G-MR product, PCIe4 product, and a 40Gb/s SERDES demonstrator. Power Integrity validation.

    • Principal Engineer
      • 2004 - 2008

      Memory and Interfaces DivisionSignal Integrity Test Lead for PlayStation3 project at Rambus. Characterization and Model Correlation on XDR Memory Subsystem, FlexIO CPU-GPU bus, and Southbridge. SI test and analysis of cost-reduction solutions.

    • Senior Member Of Technical Staff
      • 2003 - 2004

      Memory and Interfaces DivisionSignal Integrity test and analysis for NPI of XDR memory PHY.

    • Consulting Member of Technical Staff
      • 2002 - 2002

      Fiber-Optics R&DPerformance improvement and cost reduction on a 10Gb/s single-mode-fiber receiver. Fiber-Optics R&DPerformance improvement and cost reduction on a 10Gb/s single-mode-fiber receiver.

    • Telecommunications
    • 700 & Above Employee
    • Senior Development Engineer
      • 2001 - 2002

      Optics DivisionLed 10Gb/s optical-receiver development for both PIN and APD-based products. Optics DivisionLed 10Gb/s optical-receiver development for both PIN and APD-based products.

    • Semiconductors
    • 1 - 100 Employee
    • Principal Engineer/Scientist
      • 2000 - 2001

      Fiber-Optics R&DModelling of 10Gb/s fiber-optic links in Matlab and LinkSim. Characterized ICs and optical devices. Managed the test lab. Fiber-Optics R&DModelling of 10Gb/s fiber-optic links in Matlab and LinkSim. Characterized ICs and optical devices. Managed the test lab.

    • United States
    • IT Services and IT Consulting
    • 700 & Above Employee
    • Engineer/Scientist
      • 1998 - 2000

      Product R&D, Fiber-Optic Communications DivisionGigabit Ethernet transceiver and OC-48 Parallel-optics module design and test.

    • Member of Technical Staff
      • 1990 - 1998

      HP Laboratories Division, Solid-State Technology Labmm-wave amplifier, mm-wave dynamic divider, and 50GHz optical receiver design and test. 5GHz and 60GHz ISM-band wireless LAN circuit design and test.

Education

  • Stanford University School of Engineering
    BS, MS, and Ph.D., Electrical Engineering
    -

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