Chris O'Brien

Director, Product Integration at Resonant Inc., A Murata Company
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Contact Information
us****@****om
(386) 825-5501
Location
San Diego, California, United States, US

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Experience

    • United States
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Director, Product Integration
      • Aug 2022 - Present

    • Principal Process Integration Engineer
      • Oct 2020 - Jul 2022

    • United States
    • Semiconductors
    • 100 - 200 Employee
    • Senior Manager, Yield and Failure Analysis
      • Apr 2019 - Oct 2020

      Responsible for product yield from substrate to packaged test, covering 10+ key suppliers and multiple SOI CMOS processes, with focus on RF applications. Integrate IC manufacturing line with downstream module flows, identifying quality, performance, and efficiency improvements. Technical lead for customer RMAs, including management of internal Failure Analysis laboratory. My team was also responsible for developing innovative data analysis capabilities, maintaining engineering database infrastructure and automation tools, and evangelizing data science throughout the organization, Show less

    • Senior Manager, Integration
      • Aug 2014 - Mar 2019

      Responsible for product yield from substrate to packaged test, covering 10+ key suppliers and multiple SOI CMOS processes, with focus on RF applications. Technical lead for customer RMAs. Design rule manual owner for qualified processes; drive yield, quality, and manufacturing improvements through design rules and guidelines. My team was also responsible for developing innovative data analysis capabilities, maintaining engineering database infrastructure and automation tools, and evangelizing data science throughout the organization, Show less

    • Integration Manager
      • Aug 2011 - Aug 2014

    • Product Engineer
      • Apr 2010 - Aug 2011

      Responsible for yield and quality of RF switch product line on custom silicon-on-sapphire CMOS process. Managed process changes, new substrate qualification, analysis and resolution of fab related failure modes. Responsible for test coverage and limit setting to guarantee data sheet parameters.

    • Australia
    • Appliances, Electrical, and Electronics Manufacturing
    • 1 - 100 Employee
    • Device Engineer
      • Jul 2008 - Apr 2010

      Supported creation of in-house design team. Highlights of this work included • development of compressed reticle program for rapid, low-cost prototyping, • implementation of a thorough design flow, and • development and characterization of new CMOS device types and circuit blocks. Supported creation of in-house design team. Highlights of this work included • development of compressed reticle program for rapid, low-cost prototyping, • implementation of a thorough design flow, and • development and characterization of new CMOS device types and circuit blocks.

    • United States
    • Semiconductors
    • 100 - 200 Employee
    • Device Engineer
      • Jul 2006 - Jul 2008

      Responsible for process control and development for industry leading CMOS Silicon-on-Sapphire process used for high performance RF market and radiation hard space and defense applications. • process and device characterization through simulation, wafer level measurement, and DOE, • failure analysis of defective and mis-processed material; yield improvement, • process and module qualification and reliability analysis, • process monitoring and control through SPC, and • test structure design. Show less

Education

  • The University of Queensland
    PhD, Electrical Engineering (Photonics)
    2002 - 2006
  • The University of Queensland
    Bachelor, Electrical Engineering
    1998 - 2001

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