Experience

Altera

• United States
• Semiconductors
• 700 & Above Employee

• Design Engineering Supervisor

  • Jan 2012 - Present

  Managed a team on C++ device software modeling and Hardcopy migration flow in Quartus- With 6 direct reports

• Senior Design Engineer

  • Mar 2011 - Dec 2011

  Device software modeling for Digital Signal Processing (DSP) block in Quartus- Using C++, working on translation algorithms how to model and mapped the ports/parameter correctly - Implemented the feature based legality/sanity checking for sharing across device family- Lead the RTL-based generation flow for DSP soft IP Project lead for Hardcopy migration flow in Quartus- Worked with cross functional team in developing a solution to Prototype customer designs with FPGA, and then migrate the designs to Structured ASICs for volume production. Show less

• Advanced Design Engineer

  • Jun 2008 - Feb 2011

  Software R&D engineer for C++ based Quartus software- Designed System Verilog EDA netlist generation in Quartus - Developed IP Cores summary table in Quartus synthesis reportHardcopy Migration flow development - Enhancing Revision Compare (REC) tool - an in house formal verification tool

• Software Engineer

  • Jun 2007 - May 2008

  Software R&D engineer for C++ based Quartus software- EDA netlist generation tool enhancement and customer support- Memory input/output file management tool enhancement and customer suppor