Experience

Altera

• United States
• Semiconductors
• 700 & Above Employee

• Principal Engineer, R&D

  • 2011 - Present

  Technical lead for Altera 28nm, 20nm/16nm, 14nm, 10nm ASIC designs – from semiconductor technology process definition, PPA evaluation, std-cell and PVT definition to RTL2GDS, STA signoff methodology and design tape-out audit. Technical lead for Altera 28nm, 20nm/16nm, 14nm, 10nm ASIC designs – from semiconductor technology process definition, PPA evaluation, std-cell and PVT definition to RTL2GDS, STA signoff methodology and design tape-out audit.



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Design Engineer

  • 2008 - 2011

  Lead backend P&R (place and route) design team in low power, multi-well design, ESD, power grid and metal programmable design flows and methodologies. Successfully tape-out 45nm and 32nm SoC with silicon proven record. Experienced in both cell level and transistor level STA (static timing analysis). Lead backend P&R (place and route) design team in low power, multi-well design, ESD, power grid and metal programmable design flows and methodologies. Successfully tape-out 45nm and 32nm SoC with silicon proven record. Experienced in both cell level and transistor level STA (static timing analysis).



TSMC

• Taiwan
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Design Engineer

  • 2004 - 2008

  Design, develop and characterize TSMC standard-cell library. Transistor level circuit design optimizations (through new design architecture and silicon process advantages), including energy efficient architecture, power and/or performance tradeoff analysis. Apply ASIC design flow to tape-out VDSM (very deep sub-micron) test chip for circuit behavior verification on silicon. Experienced with cell base design, spice/circuit design, CMOS silicon process (from 0.35um to 28nm to FinFET), device physics and VDSM parasitic effects. Show less



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Component Design Engineer

  • 2000 - 2004

  Write regression tests extensively to simulate, validate and debug VHDL/Verilog RTL model’s logic behavior. Co-work with RTL designer for RTL bugs identification and fixing. Familiar with VHDL/Verilog language and coding. Experienced in Intel C-Sim, assembly language and IA32, IA64, multi-threading architecture. Write regression tests extensively to simulate, validate and debug VHDL/Verilog RTL model’s logic behavior. Co-work with RTL designer for RTL bugs identification and fixing. Familiar with VHDL/Verilog language and coding. Experienced in Intel C-Sim, assembly language and IA32, IA64, multi-threading architecture.