Chiu-Chun Tang

Analog Design Engineer at NSW Inc.
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Contact Information
us****@****om
(386) 825-5501
Location
Tokyo, Japan, JP
Languages
  • English TOEIC 880 Professional working proficiency
  • Japanese JLPTN1 Limited working proficiency
  • Chinese Native or bilingual proficiency

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Experience

    • IT Services and IT Consulting
    • 1 - 100 Employee
    • Analog Design Engineer
      • Oct 2022 - Present

      ・ Analog IP development (50MHz GM cell, 16GHz HSTX Driver, LED Ctrl IC) with tsmc 7nm/0.13um standard cell. ・ Analog design by using Virtuoso Cadence and Synopsys compiler. ・ PVT, Monte Carlo simulation, and create LPE netlist for pre-sim/post-sim analysis. ・ Instruct parasitics improvement to layout engineer. ・ Analog IP development (50MHz GM cell, 16GHz HSTX Driver, LED Ctrl IC) with tsmc 7nm/0.13um standard cell. ・ Analog design by using Virtuoso Cadence and Synopsys compiler. ・ PVT, Monte Carlo simulation, and create LPE netlist for pre-sim/post-sim analysis. ・ Instruct parasitics improvement to layout engineer.

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Image Sensor Product Engineer
      • Jan 2020 - Jun 2022

      1. New Product Introduction for CMOS image sensors and ASIC products. 2. Develop automation CP/FT test program to validate product performance in Wafer-scale and provide characterization, debugging, validation, and failure analysis. 3. Improve product performance and quality through collaborating with internal teams and external supply chain: Si/CF foundries and assembly house. 1. New Product Introduction for CMOS image sensors and ASIC products. 2. Develop automation CP/FT test program to validate product performance in Wafer-scale and provide characterization, debugging, validation, and failure analysis. 3. Improve product performance and quality through collaborating with internal teams and external supply chain: Si/CF foundries and assembly house.

    • Japan
    • Research Services
    • 700 & Above Employee
    • JSPS Researcher
      • Apr 2017 - Jun 2019

      1. Study terahertz photon dynamics in single-electron transistor. 2. Develop thermionic cooling device based on GaAs/AlGaAs asymmetric quantum heterostructure. 1. Study terahertz photon dynamics in single-electron transistor. 2. Develop thermionic cooling device based on GaAs/AlGaAs asymmetric quantum heterostructure.

    • Taiwan
    • Research Services
    • 700 & Above Employee
    • Postdoctoral Researcher
      • Feb 2015 - Mar 2017

      1. Develop quantum Hall dual-band Mid-/Far-infrared photodetector. 2. Experimentally discover collective plasmon modes in graphene-GaAs/AlGaAs heterostructure. 3. Investigate the acoustoelectric properties of graphene and firstly extract its acoustoelectric attenuation factor. 4. Reveal hidden Coulomb blockade signal in gate-controlled linear quantum-dot arrays. 1. Develop quantum Hall dual-band Mid-/Far-infrared photodetector. 2. Experimentally discover collective plasmon modes in graphene-GaAs/AlGaAs heterostructure. 3. Investigate the acoustoelectric properties of graphene and firstly extract its acoustoelectric attenuation factor. 4. Reveal hidden Coulomb blockade signal in gate-controlled linear quantum-dot arrays.

    • Taiwan
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Summer intern
      • Jul 2012 - Aug 2012

      1. Develop electric test patterns for detecting overlay misalignment with few nanometer accuracy. 2. Design test key to monitoring the amount of charge accumulated on devices during plasma etching process. 1. Develop electric test patterns for detecting overlay misalignment with few nanometer accuracy. 2. Design test key to monitoring the amount of charge accumulated on devices during plasma etching process.

Education

  • National Tsing Hua University
    Doctor of Philosophy (Ph.D.)
    2009 - 2014
  • National Tsing Hua University
    Bachelor’s Degree
    2005 - 2009

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