Experience

UltraSoC

• United Kingdom
• Semiconductor Manufacturing
• 1 - 100 Employee

• Hardware Engineer

  • Jul 2013 - Present



The University of Edinburgh

• United Kingdom
• Research Services
• 700 & Above Employee

• MEng Thesis

  • Jan 2012 - Jan 2013

  Design and implement a Digital Interface, using the Address Event Representation Protocol, to transfer concurrently a stream of Event Spikes between multiple Senders and Receivers. The Protocol must be able to determine the address of each input signal and route that signal to the correct receiver. The protocol was programmed in Verilog, and tested using the Xilinx ISE Web Pack. Design and implement a Digital Interface, using the Address Event Representation Protocol, to transfer concurrently a stream of Event Spikes between multiple Senders and Receivers. The Protocol must be able to determine the address of each input signal and route that signal to the correct receiver. The protocol was programmed in Verilog, and tested using the Xilinx ISE Web Pack.