Experience

Uniquify Inc

• United States
• Semiconductor Manufacturing
• 1 - 100 Employee

• Project Lead ASIC Design Engineer

  • Jul 2011 - Present

  Successfully taped out ten designs. Implemented 40nm, 32nm, and 28nm hierarchical designs from RTL to GDSII. Responsible for synthesis, floorplanning, placement, CTS, routing and optimizations to close timing, as well as power analysis and physical and logical verification. Implemented designs with complex power domains, including multi-voltage implementation and power switches. Assisted in implementing DFT. Managed/trained Jr. Engineers. Successfully taped out ten designs. Implemented 40nm, 32nm, and 28nm hierarchical designs from RTL to GDSII. Responsible for synthesis, floorplanning, placement, CTS, routing and optimizations to close timing, as well as power analysis and physical and logical verification. Implemented designs with complex power domains, including multi-voltage implementation and power switches. Assisted in implementing DFT. Managed/trained Jr. Engineers.