Experience

Dolphin Design

• France
• Semiconductor Manufacturing
• 100 - 200 Employee

• Verification Engineer

  • Jan 2021 - Present



Movidius

• United States
• Semiconductors
• 1 - 100 Employee

• Verification Engineer

  • Sep 2019 - Dec 2020

  Develop SystemVerilog tests and sequences to verify block level image IPs and their top-level integration. Create the verification plan according to the provided documentation and update it based on risks and project changes. Create the necessary verification elements to guarantee the proper sign-off. Provide coverage reports and regression results needed to complete the work packages. Propose new solutions regarding the ways in which specific components can be verified. Coordinate the Bucharest verification team of 5 people. Show less



ams AG

• Austria
• Semiconductor Manufacturing
• 700 & Above Employee

• Verification Engineer

  • Oct 2017 - Aug 2019

  Develop SystemVerilog test benches from scratch for RFIDs and consumer wireless components. Create the verification plan according to the provided documentation and update it based on risks and project changes. Verify block level components, system level parts and firmware implementation. Involved in the development of the register model and the verification of the register map using uvm_regs library with python scripts. Develop SystemVerilog test benches from scratch for RFIDs and consumer wireless components. Create the verification plan according to the provided documentation and update it based on risks and project changes. Verify block level components, system level parts and firmware implementation. Involved in the development of the register model and the verification of the register map using uvm_regs library with python scripts.



Infineon Technologies

• Germany
• Semiconductor Manufacturing
• 700 & Above Employee

• Senior Verification Engineer

  • Oct 2016 - Sep 2017

  Responsible of digital and mixed signals verification of automotive gate drivers.Check components using formal verification.Verify modules using fault injection methodologies.Create and maintain verification plan, timeline, and effort estimation.Provide coverage reports and regression results needed to complete the verification.Verification technical lead over a team of 6 people.Support for other verification teams.Mentoring of a few engineers who are now actively and independently involved in the verification process. Show less

• Verification Engineer

  • Oct 2014 - Sep 2016

  Responsible of digital and mixed signals verification of automotive gate drivers using SV and Specman/e.Create and maintain verification plan, timeline, and effort estimation.Verification technical lead over a team of 2 people.

• Verification Engineer,

  • Nov 2013 - Oct 2014

  Develop SystemVerilog tests and sequences to verify automotive multichannel gate driver.Develop from scratch Specman/e verification environment for security component. The switches were programmed using AMBA protocol.



EASYIC DESIGN

• Romania
• Semiconductors
• 1 - 100 Employee

• ASIC Verification Engineer

  • Oct 2013 - Oct 2014

• Junior ASIC Verification Engineer

  • Aug 2011 - Sep 2013



Movidius

• United States
• Semiconductors
• 1 - 100 Employee

• Verification Engineer

  • Feb 2013 - Oct 2013

  Top level (System Verilog) and software (C) verification of various multimedia processor. Top level (System Verilog) and software (C) verification of various multimedia processor.



Texas Instruments

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Junior Verification Engineer

  • Aug 2011 - Dec 2012

  Verified interconnect modules using SystemVerilog and SecurityCores using Specman/e language. These components were included into OMAP5 and OMAP6 platforms. Verified interconnect modules using SystemVerilog and SecurityCores using Specman/e language. These components were included into OMAP5 and OMAP6 platforms.