Staff Electrical Engineer

• Nov 2022 - Present

Senior Engineer (Electronics)

• Jun 2019 - Nov 2022

Communication interface module (CIM) development for Formation Flying satellites project ▪ Schematic capture and PCB layout development (Altium Designer) ▪ FPGA, DC-DC regulator, RS-422, CAN, etc ▪ PCBA testing, debugging with flight software team ▪ FPGA firmware development (VHDL for Microchip ProASIC3L) ▪ Bench test, thermal cycling test and thermal vacuum chamber test for the module in satellite ▪ Engineering reports document preparation. RF Equipment and software procurement ▪ Vector signal generator (Keysight E8267D) ▪ Analog signal generator (Keysight N5171B) ▪ Arbitrary Function generator (Tektronix AFG31252) ▪ Logic Analyzer (Keysight 16862A) ▪ Signal and spectrum Analyzer (Rhode & Schwarz FSW26) ▪ Vector signal analysis software (Keysight VSA 89600) Show less

Research Associate

• Jan 2019 - May 2019

R&D on Teraherz scanner R&D on Teraherz scanner

Senior Engineer

• Nov 2011 - Sep 2018

TeLEOS-2 Project – Evaluation of new parts to meet the requirement of new mission target and to replace obsolete parts, e.g., high speed ADC/DAC, and new IF BPF; – Schematic capturing for the prototyping of S-band transmitter and receiver; – Algorithm development and simulation for high-speed data demodulator in Synphony/Simulink; – Algorithm functionally test and verification on existing TeLEOS-1 hardware platform; TeLEOS-1 Project – Take the principle role in design and development of the hardware and software for digital receiver of TeLEOS-1 throughout engineering model, quality model and flight model phases; – Schematics design with Altium designer for TeLEOS-1, and work closely with outsource partners for PCB routing and layout; – Parts and components selection, sourcing and procurement; – Algorithm developed and simulated functionally for tracking signal distorted by Doppler effectby Matlab Simulink based on CORDIC; VHDL code verification by testbench and implementedin Microsemi Libero and Modelsim for Actel ProASIC-3L FPGA; – Lab bench testing and debugging to improve performance of of sub-modules and modules of the digital receiver; – Environment Stress Test (ESS) for the digital receiver module; – Involvement in AIT test and 3-D stackup test for the satellite; – Documentation preparation for ECP, EIP, and design documents. Show less

Research Associate

• Jul 2008 - Nov 2011

Addressable integrated initiation device – Lab setup and equipment procurement; – Prototyping of the electrical initiation device based on 8051 micro-controller; – C programming for the micro-controller; – RS-232, RS-485 interfacing; Addressable integrated initiation device – Lab setup and equipment procurement; – Prototyping of the electrical initiation device based on 8051 micro-controller; – C programming for the micro-controller; – RS-232, RS-485 interfacing;

Research Engineer

• Mar 2007 - Jun 2008

Radar signal processing board design – PCB schematic design by Mentor PADS Logic; – Analog and digital circuit design for processing the radar signal; – System Generator and VHDL for the algorithm development for Xilinx Virtex-4 FPGA; – Testing and measurement campaign for the prototype of the Doppler radar; Radar signal processing board design – PCB schematic design by Mentor PADS Logic; – Analog and digital circuit design for processing the radar signal; – System Generator and VHDL for the algorithm development for Xilinx Virtex-4 FPGA; – Testing and measurement campaign for the prototype of the Doppler radar;