Bhaskar Kumar P.
Sr. Principal verification Lead/Formal Architect at Condor Computing Corporation- Claim this Profile
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Bio
David Tran
Bhaskar has outstanding skills in quickly bringing up very complex verification environments for new co-developed RTL and firmware/software, and integrating tools from multiple sources, internal and commercial. His debug insights, quick grasp of new designs, and can-do attitude were all major enabablers allowing us to make very quick progress on a huge embedded design with stringent requirements on performance, power, and area. I have seldom come across more competent and effective Design Verification engineers.
Dr Arikatla Hazarathaiah
Bhaskar is very talented and sincere student. i am always well wisher of Bhaskar.
David Tran
Bhaskar has outstanding skills in quickly bringing up very complex verification environments for new co-developed RTL and firmware/software, and integrating tools from multiple sources, internal and commercial. His debug insights, quick grasp of new designs, and can-do attitude were all major enabablers allowing us to make very quick progress on a huge embedded design with stringent requirements on performance, power, and area. I have seldom come across more competent and effective Design Verification engineers.
Dr Arikatla Hazarathaiah
Bhaskar is very talented and sincere student. i am always well wisher of Bhaskar.
David Tran
Bhaskar has outstanding skills in quickly bringing up very complex verification environments for new co-developed RTL and firmware/software, and integrating tools from multiple sources, internal and commercial. His debug insights, quick grasp of new designs, and can-do attitude were all major enabablers allowing us to make very quick progress on a huge embedded design with stringent requirements on performance, power, and area. I have seldom come across more competent and effective Design Verification engineers.
Dr Arikatla Hazarathaiah
Bhaskar is very talented and sincere student. i am always well wisher of Bhaskar.
David Tran
Bhaskar has outstanding skills in quickly bringing up very complex verification environments for new co-developed RTL and firmware/software, and integrating tools from multiple sources, internal and commercial. His debug insights, quick grasp of new designs, and can-do attitude were all major enabablers allowing us to make very quick progress on a huge embedded design with stringent requirements on performance, power, and area. I have seldom come across more competent and effective Design Verification engineers.
Dr Arikatla Hazarathaiah
Bhaskar is very talented and sincere student. i am always well wisher of Bhaskar.
Experience
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Condor Computing Corporation
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United States
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Semiconductor Manufacturing
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1 - 100 Employee
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Sr. Principal verification Lead/Formal Architect
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Jul 2023 - Present
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Cadence Design Systems
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United States
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Software Development
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700 & Above Employee
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Solutions Architect
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Jun 2022 - Jul 2023
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Sr Principal solutions engineer
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Jun 2019 - Jul 2023
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Sr Principle Solutions Engineer
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Sep 2019 - Oct 2022
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Principle Solutions Engineer
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Jun 2016 - Sep 2019
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Aricent
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United States
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Software Development
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700 & Above Employee
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Principle Engineer
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Mar 2016 - Jun 2016
Providing Design Verification Services @ Samsung Austin Research centre Providing Design Verification Services @ Samsung Austin Research centre
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SmartPlay Technologies - An Aricent Company
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India
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IT Services and IT Consulting
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100 - 200 Employee
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Staff Asic Design Verification Engineer
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Mar 2011 - Mar 2016
Provided Design Verification Services @ Qualcomm San Diego Intel Santa Clara
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Sr Verification Engineer
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Jul 2010 - Apr 2011
Design Verification Services @ Marvell and Qualcomm Bangalore.
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Texas Instruments
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United States
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Semiconductor Manufacturing
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700 & Above Employee
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Sr Design Engineer
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Mar 2004 - Jul 2010
Front End Verification of SoCs like OMAP using simulators like Modelsim and VCS and debug tools like Novas Debussy . Scripting using Perl and tcl. Other Tools: Specman, IFV languagesKnown : C, E & PSL Other responsibilities: Power Aware RTL simulations and Power Aware GLS. Front End Verification of SoCs like OMAP using simulators like Modelsim and VCS and debug tools like Novas Debussy . Scripting using Perl and tcl. Other Tools: Specman, IFV languagesKnown : C, E & PSL Other responsibilities: Power Aware RTL simulations and Power Aware GLS.
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Teaching Assistant
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Jun 2003 - Feb 2004
Working as Teaching Assistant under Professor Samaresh Chatterji Working as Teaching Assistant under Professor Samaresh Chatterji
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Education
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2019 - 2021
University of Illinois Urbana-Champaign
Master's degree, Data science -
1998 - 2002
Jawaharlal Nehru Technological University
BTech, Electronics and Communication -
1998 - 2002
JNT University Hyderabad
Bachelors od technology, Electronics and communication Engineering
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