Balamurugan Kannappan

Principal Engineer Digital IC Design Verification at MaxLinear
  • Claim this Profile
Contact Information
us****@****om
(386) 825-5501
Location
Bengaluru, Karnataka, India, IN
Skills

Topline Score

Topline score feature will be out soon.

Bio

Generated by
Topline AI

You need to have a working account to view this content.
Join now
You need to have a working account to view this content.
Join now

Credentials

  • Performance Management: Conducting Performance Reviews
    LinkedIn
    Jun, 2023
    - Nov, 2024
  • Making Remote Work Work (getAbstract Summary)
    LinkedIn
    Apr, 2023
    - Nov, 2024
  • Project Management Skills for Leaders
    LinkedIn
    Apr, 2023
    - Nov, 2024
  • How to Commit Learning to Memory
    LinkedIn
    Mar, 2023
    - Nov, 2024
  • The Neuroscience of Strategy and Creative Leadership
    LinkedIn
    Mar, 2023
    - Nov, 2024
  • Be the Manager People Won't Leave
    LinkedIn
    Oct, 2022
    - Nov, 2024
  • Communicating in the Language of Leadership
    LinkedIn
    Oct, 2022
    - Nov, 2024
  • Leading and Motivating People with Different Personalities
    LinkedIn
    Oct, 2022
    - Nov, 2024
  • The 7 Secrets of Responsive Leadership (getAbstract Summary)
    LinkedIn
    Oct, 2022
    - Nov, 2024
  • Becoming an Impactful and Influential Leader
    LinkedIn
    Sep, 2022
    - Nov, 2024
  • The Art of Leadership (getAbstract Summary)
    LinkedIn
    Sep, 2022
    - Nov, 2024

Experience

  • MaxLinear
    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Principal Engineer Digital IC Design Verification
      • Jul 2022 - Present

      * 5G Product line - SOC DV Lead

    • Senior Staff ASIC Verification Engineer
      • Jun 2021 - Jun 2022

  • Broadcom
    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • R&D IC Design (Lead Engineer)
      • Mar 2016 - Oct 2020

      * ASIC/SOC Design Verification & Silicon Bring-up/Debug Support* Pre-Silicon Validation (Emulation) Debug

    • Sr Staff - IC Design
      • Mar 2013 - Feb 2016

      * ASIC Design Verification & Silicon Bring-up/Debug Support

    • Senior Engineer
      • Feb 2012 - Feb 2013

      * ASIC Design Verification & Silicon Bring-up/Debug Support

    • Senior Design Engineer
      • Nov 2006 - Feb 2012

      * ASIC Design Verification & Silicon Bring-up/Debug Support

  • Network Programs/Hitachi-IT (Japan)
    • Kanagawa, Japan
    • Member Of Technical Staff
      • Feb 2006 - Oct 2006

      * RTL coding * Functional verification * ASIC design * RTL coding * Functional verification * ASIC design

  • Prodapt ASIC services (Formerly Innovative Logic)
    • United States
    • IT Services and IT Consulting
    • 1 - 100 Employee
    • Senior Design Engineer
      • Jul 2005 - Feb 2006

      * ASIC design * RTL coding * ASIC design * RTL coding

  • Sona College of Technology
    • India
    • Higher Education
    • 400 - 500 Employee
    • Design Engineer
      • Jan 2004 - Jul 2005

      * Prototype Board circuit design* Tried the “Speech Recognition System” implementation with Cypress PSOC 2.0 kit. * Responsible for mentoring the new resources.

    • Research Associate
      • Dec 2002 - Dec 2003

      * Multi-Lingual Digital Organizer feasibility analysis.

Education

  • Manipal University
    Master of Science (MS), Microelectronics
    2011 - 2013
  • Sandeepani School of VLSI Design
    P.G.D.VLSI, Design
    2001 - 2002
  • University of Madras
    B.E, Electrical & Electronics Engg
    1997 - 2001

Community

You need to have a working account to view this content. Click here to join now