Rajender Baddam
FPGA Design Engineer at Celestia Satellite Test & Simulation BV- Claim this Profile
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English Professional working proficiency
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Dutch Elementary proficiency
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Telugu -
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Hindi -
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Bio
Jos Teunissen
During this period Rajender did his master thesis and contributed to the development and realization of a key-component in a deterministic embedded system. Rajender is focused on delivering high quality, which is an important asset to us having to deliver in the automotive industry. Rajender was educated by the design-team of high-qualified engineers, hardware architect and system architect. Knows the Digital Design-flow from architectural specification, design methodology and VHDL implementation and finally simulation. The complete design flow. Rajender got a good insight in the thesis assignment; he translated PhD thesis into the IC specification and design flow. Finally his results will end some day into silicon. His quality and carry out of the assignment was very good, and he showed a lot of self-initiatives to come with a better solution than the engineers and mentor thought. And he showed an excellent commitment in the assignment during the whole period of his internship. I believe that Rajender, is well educated and trained at the University of Lund and at NXP semiconductors, that he is able to start a carrier as a Digital Design Engineer for silicon as well for FPGA designs.
Jos Teunissen
During this period Rajender did his master thesis and contributed to the development and realization of a key-component in a deterministic embedded system. Rajender is focused on delivering high quality, which is an important asset to us having to deliver in the automotive industry. Rajender was educated by the design-team of high-qualified engineers, hardware architect and system architect. Knows the Digital Design-flow from architectural specification, design methodology and VHDL implementation and finally simulation. The complete design flow. Rajender got a good insight in the thesis assignment; he translated PhD thesis into the IC specification and design flow. Finally his results will end some day into silicon. His quality and carry out of the assignment was very good, and he showed a lot of self-initiatives to come with a better solution than the engineers and mentor thought. And he showed an excellent commitment in the assignment during the whole period of his internship. I believe that Rajender, is well educated and trained at the University of Lund and at NXP semiconductors, that he is able to start a carrier as a Digital Design Engineer for silicon as well for FPGA designs.
Jos Teunissen
During this period Rajender did his master thesis and contributed to the development and realization of a key-component in a deterministic embedded system. Rajender is focused on delivering high quality, which is an important asset to us having to deliver in the automotive industry. Rajender was educated by the design-team of high-qualified engineers, hardware architect and system architect. Knows the Digital Design-flow from architectural specification, design methodology and VHDL implementation and finally simulation. The complete design flow. Rajender got a good insight in the thesis assignment; he translated PhD thesis into the IC specification and design flow. Finally his results will end some day into silicon. His quality and carry out of the assignment was very good, and he showed a lot of self-initiatives to come with a better solution than the engineers and mentor thought. And he showed an excellent commitment in the assignment during the whole period of his internship. I believe that Rajender, is well educated and trained at the University of Lund and at NXP semiconductors, that he is able to start a carrier as a Digital Design Engineer for silicon as well for FPGA designs.
Jos Teunissen
During this period Rajender did his master thesis and contributed to the development and realization of a key-component in a deterministic embedded system. Rajender is focused on delivering high quality, which is an important asset to us having to deliver in the automotive industry. Rajender was educated by the design-team of high-qualified engineers, hardware architect and system architect. Knows the Digital Design-flow from architectural specification, design methodology and VHDL implementation and finally simulation. The complete design flow. Rajender got a good insight in the thesis assignment; he translated PhD thesis into the IC specification and design flow. Finally his results will end some day into silicon. His quality and carry out of the assignment was very good, and he showed a lot of self-initiatives to come with a better solution than the engineers and mentor thought. And he showed an excellent commitment in the assignment during the whole period of his internship. I believe that Rajender, is well educated and trained at the University of Lund and at NXP semiconductors, that he is able to start a carrier as a Digital Design Engineer for silicon as well for FPGA designs.
Experience
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Celestia Satellite Test & Simulation BV
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Netherlands
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Information Services
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FPGA Design Engineer
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Feb 2017 - Present
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INCAS³
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United Kingdom
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Legal Services
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1 - 100 Employee
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FPGA Engineer
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Dec 2010 - Jan 2017
Currently working on projects for the radiation detection research line within INCAS³. Expertise includes hardware programming, targeting Field Programmable Gate Arrays (FPGA’s) for digital signal processing and embedded processing applications. Develops prototypes using FPGA’s for slow and fast radiation sensors. Currently working on projects for the radiation detection research line within INCAS³. Expertise includes hardware programming, targeting Field Programmable Gate Arrays (FPGA’s) for digital signal processing and embedded processing applications. Develops prototypes using FPGA’s for slow and fast radiation sensors.
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NXP
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Consumer Services
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1 - 100 Employee
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Design and Analysis of DMA controller on Network on chip
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Jan 2009 - Oct 2009
Future embedded systems use Network on Chip technology. On this network, tiles of sub-embedded systems are connected. For inter-tile communication over the network, a communication module is required between the sub embedded system and the network–FIFO. The module is called, Communication Assist, which is similar to a DMA controller. This module has been designed by a Hatley&Pirbhai design methodology and implemented in VHDL language. Future embedded systems use Network on Chip technology. On this network, tiles of sub-embedded systems are connected. For inter-tile communication over the network, a communication module is required between the sub embedded system and the network–FIFO. The module is called, Communication Assist, which is similar to a DMA controller. This module has been designed by a Hatley&Pirbhai design methodology and implemented in VHDL language.
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Education
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Lunds Tekniska Högskola
Masters in Science, System On Chip -
2002 - 2006
Jawaharlal Nehru Technological University
Bachelors in Technology(Btech), Electronics and Communications
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