Avnita Pal

Design and Verification Engineer at Silicon Interfaces
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Contact Information
us****@****om
(386) 825-5501
Location
IN
Skills

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Credentials

  • Certification in MATLAB
    Anand Engineering College

Experience

  • Silicon Interfaces
    • Information Technology & Services
    • 1 - 100 Employee
    • Design and Verification Engineer
      • May 2019 - Present

  • Banasthali Vidyapith
    • India
    • Higher Education
    • 700 & Above Employee
    • M.Tech in VLSI Design
      • Jul 2013 - Aug 2015

      Done Masters In VLSI design from Banasthali Vidyapith University Done Masters In VLSI design from Banasthali Vidyapith University

  • BARC
    • India
    • Research Services
    • 700 & Above Employee
    • Internship Trainee
      • Jul 2014 - Jul 2015

      Have experienced in FPGA, OrCAD Tool, HDL Languages-Verilog, System Verilog, also Matlab. Have experienced in FPGA, OrCAD Tool, HDL Languages-Verilog, System Verilog, also Matlab.

Education

  • Banasthali Vidyapith
    Master of Technology - MTech, VLSI Design
    2013 - 2015
  • Anand Engineering College(SGI)
    Bachelor's Degree in Electronics & Instrumentation, Electronics and Instrumentation
    2009 - 2013

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