Experience

Altered Silicon, Inc.
• United States
• Software Development
• 1 - 100 Employee
• CTO

  • Oct 2018 - Present

HashMax
• Singapore
• Financial Services
• 1 - 100 Employee
• CTO

  • Dec 2017 - May 2018

Entrepreneur First
• United Kingdom
• Venture Capital and Private Equity Principals
• 400 - 500 Employee
• EF9 Cohort member

  • Oct 2017 - Nov 2017


ARM

• United Kingdom
• Semiconductor Manufacturing
• 700 & Above Employee

• • Mar 2017 - Jul 2017

• • Aug 2015 - Mar 2017



Imagination Technologies

• United Kingdom
• Semiconductor Manufacturing
• 700 & Above Employee

• • Apr 2014 - Aug 2015

  Working on different aspects of TPU (Texture processing unit) of the latest GPU Rogue architecture. Write specification, design VHDL RTL, verify with UVM to achieve 100% functional and code coverage. Timing closure, area reduction, power savings with clever coding and architecture.

• • Apr 2012 - Mar 2014

  Mainly worked on TAG (Texture address generator) module. Get introduced to different texture types, texture formats, filtering types, etc. Read specification, write VHDL RTL, verify through both UVM module level and Top RTL level simulations, finalize verification by a complete regression suite.



Melexis

• Belgium
• Semiconductor Manufacturing
• 700 & Above Employee

• Junior Digital Designer

  • Feb 2011 - Dec 2011

  Responsible for designing/verifying digital components of mixed signal ASIC. Chip's digital part is composed of a SoC around internally designed 16bit microprocessor. 1) Verified couple of IPs within SoC with combination of C/Assembly code and System Verilog Assertions. 2) Shifted 16bit microprocessor (like in old times, it was draw in schematics) to Verilog RTL. During the process, learned how to implement (on gate level) Carry look-ahead adder, Radix-4 booth recoding multiplication, restoring unsigned division and non-restoring signed division. The project was finalized by a formal verification with Cadence Conformal, confirming functional equivalence of schematics(generated netlist) and written RTL. Show less

• Intern

  • Mar 2010 - Sep 2010

  As a placement student at R&D Department of ARM Ltd, Cambridge, UK I was working on a project called for future explorations on many-core systems. The whole design (32 cores) has been emulated (Verilog RTL) on a single Virtex-5 FPGA. Available benchmarks were executed providing initial data for future research. As a placement student at R&D Department of ARM Ltd, Cambridge, UK I was working on a project called for future explorations on many-core systems. The whole design (32 cores) has been emulated (Verilog RTL) on a single Virtex-5 FPGA. Available benchmarks were executed providing initial data for future research.