Arpan Chakraborty

Undergraduate Engineering Student at Jadavpur University
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Contact Information
us****@****om
(386) 825-5501
Location
Kaliyaganj, West Bengal, India, IN
Languages
  • English Full professional proficiency
  • Bengali Full professional proficiency
  • Hindi Elementary proficiency

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Experience

    • Higher Education
    • 700 & Above Employee
    • Undergraduate Engineering Student
      • Jun 2020 - Present

      Final Year Project - Design, Layout of an Ultra Low Noise LDO with a PSRR of -40dB within a Bandwidth of 1MHz range for Low power Applications. Tools and Technologies Used- 180nm TSMC Node, Cadence Virtuoso, Cadence Spectre, LTSpice Final Year Project - Design, Layout of an Ultra Low Noise LDO with a PSRR of -40dB within a Bandwidth of 1MHz range for Low power Applications. Tools and Technologies Used- 180nm TSMC Node, Cadence Virtuoso, Cadence Spectre, LTSpice

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Analog Validation Engineer Intern
      • May 2023 - Jul 2023

      I have done three Projects during my Internship Period . Details are as follows 1) Strain Sensitivity Analysis of PNP AND NPN Bipolars in Series Reference Test Chip. 2) PCB Development of Buried Zener Based Shunt Voltage Reference Testchip. (Fabrication and Assembly was also done during my Internship Period) 3) A Novel Approach to design a Power Supply Noise Cleaner Circuit with a PSRR of -40 dB within a Bandwidth of 0.1 Hz to 1MHz . I have done three Projects during my Internship Period . Details are as follows 1) Strain Sensitivity Analysis of PNP AND NPN Bipolars in Series Reference Test Chip. 2) PCB Development of Buried Zener Based Shunt Voltage Reference Testchip. (Fabrication and Assembly was also done during my Internship Period) 3) A Novel Approach to design a Power Supply Noise Cleaner Circuit with a PSRR of -40 dB within a Bandwidth of 0.1 Hz to 1MHz .

    • India
    • Research Services
    • 200 - 300 Employee
    • RF Design Intern
      • May 2022 - Jul 2022

      •Design of a miniaturized Stepped Impedance RF lowpass filter with Open circuit Stubs at Cutoff around 2.5 GHz . Tools & technologies used: Keysight ADS, HFSS. •Design of a miniaturized Stepped Impedance RF lowpass filter with Open circuit Stubs at Cutoff around 2.5 GHz . Tools & technologies used: Keysight ADS, HFSS.

Education

  • Jadavpur University
    Bachelor of Engineering - BE, Electrical and Electronics Engineering
    2020 - 2024
  • Atreyee DAV Public School
    High School, Science
    2017 - 2019
  • Atreyee DAV public school
    Intermediate, CGPA 10
    2016 - 2017
  • The Atreyee English Medium School
    2004 - 2009

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