Experience

Tokyo Institute of Technology

• Japan
• Higher Education
• 500 - 600 Employee

• Specially Appointed Assistant Professor

  • Aug 2022 - Present



IEEE

• United States
• Non-profit Organizations
• 700 & Above Employee

• IEEE Senior Member

  • Oct 2019 - Present



Ericsson

• Sweden
• Telecommunications
• 700 & Above Employee

• Radio SoC System Designer

  • Nov 2021 - Jul 2022

• Experienced Researcher

  • Oct 2018 - Oct 2021



Tokyo Institute of Technology

• Japan
• Higher Education
• 500 - 600 Employee

• Post Doctoral Researcher

  • Apr 2017 - Jul 2018



Tokyo Institute of Technology

• Research Services
• 300 - 400 Employee

• Ph.D.

  • Apr 2012 - Mar 2017

  Fractional-N PLL design - Development of fractional-N PLL with low-inband noise.Fully-synthesizable CDR design - Investigated the feasibility of entirely synthesizing CDR (Clock Data Recovery circuit). - Successfully implemented the CDR in 28nm FD SOI process. - World's first fully-synthesizable CDR. Low-power High-purity VCO design - Investigation of high efficiency VCOs. - Development of pulse-drive mechanism for high efficiency. PVT-robust high-efficiency VCO design - Study of the effects of PVT on VCOs. - Development of bias mechanism for highly robust VCO without compromising high efficiency.

• Chair(2013-2014), ieee student branch of tokyotech

  • Apr 2013 - Apr 2014

  Organising student paper contest (SPC) for the year 2013 Organising career talk and award ceremony for SPC 2013 - Opportunities and challenges in the current job market - an industry perspective

• Research Student

  • Apr 2011 - Apr 2012

  Low power VCO design, 3-D Inductor Design, Investigation of I-Q calibration for homodyne receiver