Firmware Engineer

• Jun 2016 - Present

My role in the company was to develop the firmware of the connected glass from scratch. I worked alone but I had a lot of interaction with the design, software and data science teams to insure that the glass would work in the best way possible. My tasks were to design the system architecture and to develop the firmware in C language. The firmware development was separated in different activities:- Driver development (accelerometer, memory, ultrasonic sensor).- Bluetooth communication specification and development.- Feature specification and development (liquid level measurement).- Firmware development for the different beacon we were using.

ingénieur firmware

• May 2016 - Present

Consultant

• Jan 2016 - May 2016

I was working as a consulting engineer for this company and my main mission was to work for Nokia in its telecommunication department. The mission was to help with the elaboration of an Ethernet modem interface for point-to-point radio communication with 10 GB/s of maximal band width (implemented on a Virtex 7 FPGA). My Primary activities included RTL design using VHDL, as well as simulation and verification.Technical environment :- VHDL- Vivado, Modelsim- Target 7 VIRTEX I was working as a consulting engineer for this company and my main mission was to work for Nokia in its telecommunication department. The mission was to help with the elaboration of an Ethernet modem interface for point-to-point radio communication with 10 GB/s of maximal band width (implemented on a Virtex 7 FPGA). My Primary activities included RTL design using VHDL, as well as simulation and verification.Technical environment :- VHDL- Vivado, Modelsim- Target 7 VIRTEX

Intern

• Apr 2015 - Sep 2015

The mission of the internship was to create a generic interconnection system. My role was to design and realize the architecture of the system based on the requirement given by the FPGA team. The mission can be separated in three part:- Realization of a design report.- Architecture implementation.- Verification using SystemVerilog.Technical environment : - Word, PowerPoint, Visio- Verilog, SystemVerilog- Cockpit, Modelsim, Vivado The mission of the internship was to create a generic interconnection system. My role was to design and realize the architecture of the system based on the requirement given by the FPGA team. The mission can be separated in three part:- Realization of a design report.- Architecture implementation.- Verification using SystemVerilog.Technical environment : - Word, PowerPoint, Visio- Verilog, SystemVerilog- Cockpit, Modelsim, Vivado

School project

• Oct 2014 - May 2015

Creation of a persistence of vision globe. It required RTL design and VHDL coding on a FPGA (ZYNQ) for the image processing and an embedded linux for the controller. 2nd prize in the DIGILENT Design Contest 2015:• Design of the FPGA part:- Design of the architecture of the display part;- Design of the architecture of the GPU;- Design of the architecture of the motor controller;- Implementation of these architectures on Zynq 7010;- encapsulation in an IP;• Design of the embedded software:- Conception of the drivers;- Installation of the linux kernel on a Cortex A9;- Creation of a the demonstration applications in C;• Manufacturing of the globe (mechanical part and connector)Technical environment :- VHDL- Vivado, Modelsim- C, Linux

Intern

• Sep 2013 - Aug 2014

The mission of the internship was to create a modulator for the DVB-S2X standard used for satellite communication. We were two intern on this project. My role was mainly to design the architecture and implement the system. I also had to work on a MatLab model used for the simulation and verification•State of the art :- Study of existing modulators for the DVB-S2 standard;• Design of MatLab model:- Design of the model for the modulator in MatLab;- Addition of the functions of the DVB-S2X standard;- Simulation of the model• Modulator design:- Design of architecture;- Implementation in VHDL;- Simulation and verification bitwise compared with MatLab results;- Synthesis;- Place and route;Technical environment :- VHDL- Vivado, Modelsim- MatLab- Target 7 VIRTEX