Experience

Sol Clarity

• United States
• Solar Electric Power Generation
• 1 - 100 Employee

• Co-Founder, CTO

  • Jan 2021 - Present



Wood Mackenzie Power & Renewables

• United Kingdom
• Renewable Energy Semiconductor Manufacturing
• 1 - 100 Employee

• Research Analyst for Solar Technologies

  • Feb 2022 - Jul 2023



Boston University

• United States
• Higher Education
• 700 & Above Employee

• Visiting Researcher

  • Apr 2020 - Sep 2020

• PHD Candidate

  • Sep 2016 - Apr 2020

• Research Assistant

  • Dec 2014 - Sep 2016

• Master Student

  • Aug 2014 - May 2016

  >Research assistant - self cleaning solar panels>Teaching Assistant - Solar Energy Systems

• Teaching Assistant

  • Jan 2015 - May 2015



Indian Institute of Technology, Madras

• India
• Higher Education
• 700 & Above Employee

• Undergraduate Research Intern

  • Jan 2013 - Apr 2014

  *The aim of the project is to use Bluespec System Verilog to implement a simple 5 stage pipeline processor supporting a subset of the latest RISC-V ISA. *The 5 stages of the pipeline will be fetch, decode, execution, memory and write-back. * Since the processor is being targeted for an FPGA implementation, cache/memory development is not required. On board DRAM/flash memories will be used to load and store data. Forwarding logic and other optimizations which can improve the efficiency (in terms of MIPS) of the processor can also be taken up based on the time-frame of the project and the progress made . * A middle milestone for the project would be to have a full bluespec based environment to run simulations and test-cases. *A final end to the project would be to run the same set of simulations and more on Artix-7 FPGA board. Show less