Ankit Garg

Senior Design Engineer at Cadence Design Systems (India) Pvt. Ltd.
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Contact Information
us****@****om
(386) 825-5501
Location
Bengaluru, Karnataka, India, IN
Languages
  • English -
  • Hindi -
Skills

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Credentials

  • Quantus Transistor-Level T1: Overview and Technology Setup v19.1 Exam
    Cadence Design Systems
    May, 2020
    - Nov, 2024
  • Tensilica Xtensa NX Processor Fundamentals v9.2 Exam
    Cadence Design Systems
    May, 2020
    - Nov, 2024
  • Genus Synthesis Solution with Stylus Common UI v19.1 Exam
    Cadence Design Systems
    Apr, 2020
    - Nov, 2024
  • Innovus Block Implementation with Stylus Common UI v19.1 Exam
    Cadence Design Systems
    Apr, 2020
    - Nov, 2024
  • Low-Power Synthesis Flow with Genus Stylus Common UI v19.1 Exam
    Cadence Design Systems
    Apr, 2020
    - Nov, 2024
  • Voltus Power-Grid Analysis and Signoff with Stylus Common UI v19.1 Exam
    Cadence Design Systems
    Apr, 2020
    - Nov, 2024

Experience

  • Cadence Design Systems (India) Pvt. Ltd.
    • India
    • 1 - 100 Employee
    • Senior Design Engineer
      • Dec 2018 - Present

  • Graphene Semiconductor Services Pvt Ltd.
    • India
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Physical Design Engineer
      • Dec 2017 - Dec 2018

  • RV-VLSI VLSI and Embedded Systems Design Center
    • India
    • Education Administration Programs
    • 100 - 200 Employee
    • Trainee
      • Mar 2017 - Sep 2017

      Backend Implementation of the Logic DesignDesign was started with the floorplanning for 40 nm Technology node. Design used 34 macros, 42k standard cells, 6 clocks and 6 metal layers. Supply voltage for the design was 1.1 volt and max. IR drop allowed was 5 % of the supply voltage. ME5 and ME6 metal layer were used for power straps and optimization of IR drop and placement of the standard cells were done by IC Compiler tool (Synopsys). Removal of the congestion was done by increasing the spacing between the macros depending on the no. of pins in the macros, inserting the placement blockages between the macros and core area. STA was done. Analysis of the timing reports for all timing path (reg to reg, in to reg, reg. to out, in to out) and fixing of all the setup and hold timing violations. CTS was done to drive high fanout. Effects of the clock skew, OCV, CRPR on timing, timing analysis of latch, DRC and LVS cleaned.

Education

  • Indian Institute of Technology, Madras
    M.Tech, Solid State Electronics
    2014 - 2016
  • N.R.E.C. College Khurja (Bulandshahr) Ph.No.05738-247834, 245132
    Master's degree, Physics
    2008 - 2010
  • Central Board of Secondary Education
    12th, Physical Sciences
    -
  • Central Board of Secondary Education
    10th, Physical Sciences
    -
  • N.R.E.C. College Khurja (Bulandshahr) Ph.No.05738-247834, 245132
    Bachelor's degree, Physical Sciences
    -

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