Andreas Rytlig
Senior ASIC/FPGA Design Engineer / Project Lead at Zeuxion- Claim this Profile
Contact Information
us****@****om
(386) 825-5501
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Location
Copenhagen, Capital Region, Denmark, DK
Languages
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Danish -
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English -
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Experience
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Zeuxion
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Denmark
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Computer Networking Products
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1 - 100 Employee
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Senior ASIC/FPGA Design Engineer / Project Lead
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Sep 2010 - Present
Overview: Senior FPGA/ASIC developer with focus on communication equipment, including schemes such as Ethernet, FlexE, FlexO, OTN. Design of systems with soft core processors like NIOS and MicroBlaze along with custom communication protocols. Furthermore, various work involving DSP functionality in FPGA's and external ADC/DAC interfacing. Project lead with experience using agile methodology with JIRA. Main responsibilities: Project Lead, RTL design and FPGA backend, regression testing, documentation. Primary languages: VHDL/SystemVerilog and C/TCL/python Show less
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Delta
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United Kingdom
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Professional Training and Coaching
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1 - 100 Employee
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Student
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Aug 2006 - Jun 2010
Production of optical thin film coatings. Production of optical thin film coatings.
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Education
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Danmarks Tekniske Universitet
M.Sc., Telecommunications -
Allerød Gymnasium
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