Experience

Interra Systems

• United States
• Software Development
• 200 - 300 Employee

• Senior EDA Engineer

  • Aug 2011 - Present

  1. IODV Connectivity Checks in IFV : SOC level IO-pad connectivity checks (Assertion based) in IFV.2. ECO on Layout netlist and LEC between different netlist : ECO on RCPLE and Layout netlist and LEC of r2r, r2n,n2n in different level of front-end VLSI design.3. TI-Autogen PRP flow : PRP(Parameter Reference Profile) flow development, enhancement, issue fixing and support.Scripting Language : Perl4. Opcode to TDL Flow Development : Hex to TDL (Test Description Language) flow developed.Scripting Language : Perl5. Releasing IP’s in TI front end design flow - FLOW3 (Flow3-Factory): Project Setup generation, CAD Models Installation,IP-tracking and maintenance of clearcase config spec, Debugging and fixing issues in different flow3 features given below : Compilation & Elaboration-----NCSim RTL Rule Checks-----Spyglass Synthesis-----RC &DC Equivalence Check-----LEC ATPG------ET & Tetramax6. Working in Conformal Low Power (CLP) and TIPM : Creating CLP dofile(command file), cpf file and Spyglass TIPM checks for IPs. Show less

• Design Engineer

  • Apr 2011 - Present

  VLSI Design & ServicesEDA Tools



Texas Instruments

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Flow3 Factory

  • 2011 - 2012

  1. Releasing IP’s in TI front end design flow - FLOW3 (Flow3-Factory) : Project Setup generation, CAD Models Installation, IP tracking and maintenance of clearcase config spec, Debugging and fixing issues in different flow3 features given below : Features CAD tools used Compilation & Elaboration NCSim RTL Rule Checks Spyglass – Atrenta Logical synthesis RC-Cadence & DC-Synopsys Equivalence Check LEC--Cadence ATPG ET-Cadence & Tetramax-Synopsys 2. Working in Conformal Low Power (CLP) and TIPM : Making CLP dofile(command file), CPF files and Spyglass TIPM checks for IPs. Show less