Experience

Vayavya Labs Pvt. Ltd.

• India
• IT Services and IT Consulting
• 100 - 200 Employee

• SOC Modelling Engineer

  • Feb 2023 - Present

• SOC Modelling Intern

  • Aug 2022 - Jan 2023

  Project Title: Modeling LC3 RISC core using SystemCDescription:● The project involved implementing an Instruction Set Simulator for LC3 along with a memory model using C++/SystemCProject Title: Training at Vayavya LabsEnvironment: C++, SystemC, TLM 2.0, Linux● Worked on various C++/SystemC assignments● Implemented SystemC models of Counter and DMA controllers● Created/Extended TLM 2.0 examples of SystemC modelsProject Title: Software execution demo on RISC V Virtual PlatformDescription:● We used an existing open-source implementation of of RISC V platform implemented in SystemC/TLM to execute embedded software Show less



Tejas Networks

• India
• Telecommunications
• 700 & Above Employee

• Intern

  • Feb 2022 - Jun 2022

  Responsibility : Worked on the following L2 and Edge technologies ● Ethernet Ring Protection Switching (ERPS) ● LAG (Link Aggregation Protocol) ● ELINE/ELAN ● Ingress and Egress QOS ● Gigabit Passive Optical Network (GPON) Responsibility : Worked on the following L2 and Edge technologies ● Ethernet Ring Protection Switching (ERPS) ● LAG (Link Aggregation Protocol) ● ELINE/ELAN ● Ingress and Egress QOS ● Gigabit Passive Optical Network (GPON)