Allen Timothy Chang

CAD Engineer in Embedded Non-volatile Memory Design Division at TSMC
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Contact Information
us****@****om
(386) 825-5501
Location
Taiwan, TW
Languages
  • English Native or bilingual proficiency
  • Chinese Professional working proficiency

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Bio

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Credentials

  • edX Verified Certificate for Python Basics for Data Science
    edX
    Nov, 2020
    - Nov, 2024
  • Introduction to TensorFlow for Artificial Intelligence, Machine Learning, and Deep Learning
    Coursera
    Jul, 2020
    - Nov, 2024

Experience

    • Taiwan
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • CAD Engineer in Embedded Non-volatile Memory Design Division
      • Sep 2020 - Present

      Currently write Python and Perl scripts to automate generation of IP design kits, including the quality control check of these kits. Create scripts to check consistency of CP test flows of embedded memory controllers. Study and modify scripts of several thousand lines of code that lack both documentation and in-code comments from authors who are no longer reachable.

    • Biosensor and Analog Customer Application Engineer (CAE)
      • Jul 2017 - Sep 2020

      As biosensor customer application engineer, served as main interface to customers and universities outside of Taiwan, supporting them with biosensor semiconductor chips and answering questions on using the chips. As internal test engineer, examined the pH sensitivity characteristics of the biosensors. Additionally, applied different types of surface chemistries directly on chip to see their impact on the biosensor response. Wrote Matlab code to analyze the real-time response from a mega-pixel biosensor array.As analog customer application engineer, wrote a detailed document regarding the implementation of analog cells in n5 technology to complement the training slides made by a colleague in order to enhance communication to customer users. Also supported universities with n40HV mixed signal tape outs, answering questions about the design documents and design rule violations.

    • Analog Customer Application Engineer (CAE)
      • Mar 2015 - Jul 2017

      Compiled and assured quality of n16 and n10 FinFET analog layout and circuitry implementation recommendations proposed from internal designers for customer's reference. This includes MOS and BJT arrays used in amplifiers and bandgap circuits. Gave on-site and teleconference presentations to customers regarding the recommendations.Helped customers debug their circuits and answered customer's analog implementation questions with the assistance of internal designers.Drafted SOW (Statement of Work) for a IP project that a customer outsourced to my company, ironing out ambiguities in the IP specifications and delivery terms. Created automation scripts in Perl to simulate all the IP's test vectors. As project manager, ensured internal designers met schedule in completing the IP.As part of company's CSR (Corporate Social Responsibility) in providing universities free foundry “shuttles,” researched and provided a university's analog group with foundry design docs, PDKs, and libraries. Helped the university to resolve their issues in taping out their designs and properly following the terms and conditions of the shuttle service.

    • Principal RD Fabrication Engineer, MEMS program
      • Sep 2007 - Mar 2015

      Worked with motion sensor and BioMEMS customers to bring their devices into mass production. This includes evaluating the customer's physical spec proposals and providing process fabrication flow and counter spec proposals to make their devices more manufacturable in a CMOS-based semiconductor foundry. Additionally, co-worked with the module and manufacturing teams to improve the process margins of a fabrication flow and develop workarounds to the flow if the margin issues cannot be resolved.

    • Senior Product Engineer
      • Sep 2005 - Sep 2007

      Helped customers with their digital circuit design issues from a process perspective. This included analyzing functional tests and WAT results, examining the layouts, and running Spice simulations to help understand the issue. Additionally, validated certain types of internal design rules and process-based design optimization tools with the assistance of Perl and shell scripts. Technology nodes that I mainly serviced include n90, n65, and n55.

Education

  • Stanford University
    Graduate Certificate (Stanford Center for Professional Development), Electrical Engineering
    2021 - 2023
  • University of Illinois Urbana-Champaign
    BS, Electrical Engineering
    -
  • University of California, Berkeley
    Master of Science - MS, Electrical Engineering
    -

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