Alessio Gravina
FPGA Designer at Sanitas EG- Claim this Profile
Contact Information
us****@****om
(386) 825-5501
Gold Feature
Click to upgrade to our gold package
for the full feature experience.
Location
Milan, Lombardy, Italy, IT
Languages
-
Italiano Native or bilingual proficiency
-
Inglese Professional working proficiency
Topline Score
Topline score feature will be out soon.
Bio
Generated by
Topline AI
You need to have a working account to view this content.
Join now
You need to have a working account to view this content.
Join now
Experience
-
Sanitas EG
-
Italy
-
Software Development
-
1 - 100 Employee
-
FPGA Designer
-
May 2004 - Present
VHDL & Verilog Programming. Embedded systems design, development and deployment. VHDL & Verilog Programming. Embedded systems design, development and deployment.
-
-
-
COSYSPACE IASF Milano
-
Milano, Italia
-
Collaborator
-
May 2004 - Present
-
-
-
-
Graduate Student
-
Jul 2009 - Apr 2010
-
-
Education
-
1999 - 2009
Università degli Studi di Milano
Master, Physics -
1993 - 1998
Liceo Scientifico S. Allende
Diploma
Community
You need to have a working account to view this content.
Click here to join now
