Alessandro Danese

Software Engineer at Meteomatics
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Contact Information
us****@****om
(386) 825-5501
Location
St Gallen, Switzerland, CH
Languages
  • Italiano Native or bilingual proficiency
  • Inglese Full professional proficiency
  • Tedesco Limited working proficiency

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Experience

    • Switzerland
    • Information Services
    • 1 - 100 Employee
    • Software Engineer
      • Oct 2019 - Present

      Role: development and optimization of algorithms and software architectures for forecasting and processing of large amount of weather data. • Increased server query response time up to 30% by designing and co-leading the implementation of a new approach to compute weather parameters (C++). • Increased server query response time by 20% by optimizing computationally intensive algorithms (C++). • Made server API front-ends reliable and easy to extend by designing, implementing, and verifying a new parsing logic for incoming API requests (C++). • Designed and leaded the development of a software architecture capable of efficiently receiving, storing, and managing millions of weather alerts/observations from airports and weather stations worldwide (Python, C++, geographic databases). • Reviewed code developed by other developers and provided feedback to ensure best practices (C++). Role: mentoring CPP-teams on good practices for software design, development, and testing. • Organized and gave tech talks about SOLID principles, design patterns, unit-tests, and test-coverage. Role: scrum-master in a team of 7 people. • Conducting daily meetings to monitor the progress of the ongoing tasks, address raising issues, and ensuring timely completion within the expected deadlines. Role: technical support for customers and sales. Show less

    • Italy
    • Higher Education
    • 700 & Above Employee
    • Postdoctoral Researcher
      • Jan 2018 - Oct 2019

      Research Project: Application of semi-formal approaches for the resolution of firmware security vulnerabilities. • Defined a methodology to automatically remove an identified vulnerability from a firmware source code without modifying other functionalities. Research Project: Application of semi-formal approaches for the resolution of firmware security vulnerabilities. • Defined a methodology to automatically remove an identified vulnerability from a firmware source code without modifying other functionalities.

    • Italy
    • Higher Education
    • 700 & Above Employee
    • Contract Professor - Operating Systems
      • Jan 2018 - Sep 2019

      Main lecturer for the course: “Operating Systems (Laboratory)”, BSc degree in Computer Science (6 ECTS) Designed and implemented an educational open-source Linux-like Operating System (C, Assembly). Public repository: https://mentos-team.github.io/ Gave lectures about C programming language, system calls, and memory/task management in Linux. Main lecturer for the course: “Operating Systems (Laboratory)”, BSc degree in Computer Science (6 ECTS) Designed and implemented an educational open-source Linux-like Operating System (C, Assembly). Public repository: https://mentos-team.github.io/ Gave lectures about C programming language, system calls, and memory/task management in Linux.

    • Italy
    • Research Services
    • 700 & Above Employee
    • Teaching Assistant - Computer Science
      • Sep 2018 - Dec 2018

      Main lecturer for the course: “Computer Science (Laboratory)”, BSc degree in Mechanical Engineering (6 ECTS) Gave lectures on design and synthesis of digital circuits, C programming language, and MATLAB (C). Main lecturer for the course: “Computer Science (Laboratory)”, BSc degree in Mechanical Engineering (6 ECTS) Gave lectures on design and synthesis of digital circuits, C programming language, and MATLAB (C).

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Researcher
      • Jul 2017 - Dec 2017

      Research division: INTEL Strategic CAD LABs Decreased the emulation time up to 20% of industrial-size hardware components for FPGA platforms by implementing a new approach automatically removing the unnecessary hardware components for a functionality under test (System Verilog). Research division: INTEL Strategic CAD LABs Decreased the emulation time up to 20% of industrial-size hardware components for FPGA platforms by implementing a new approach automatically removing the unnecessary hardware components for a functionality under test (System Verilog).

    • United States
    • Higher Education
    • 700 & Above Employee
    • Visiting PHD Student
      • Jul 2016 - Dec 2016

      Research Project: Application of semi-formal approaches for the identification of firmware security vulnerabilities (Mentor: Valeria Bertacco). • Defined a new methodology to automatically identify the execution paths of a firmware that most likely can be exploited by attackers to introduce a security vulnerability in an SoC. (Project supported by C-FAR, one of the six research centers sponsored by MARCO and DARPA). The defined strategy was selected and presented in an internal tech talk at INTEL Strategy CAD LABs. Show less

Education

  • Università degli Studi di Verona
    Doctor of Philosophy - PhD, Informatica
    2015 - 2018
  • Università degli Studi di Verona
    Laurea Magistrale LM in scienze e tecnologie informatiche, Embedded Systems
    2011 - 2014
  • Università degli Studi di Verona
    Laurea L in Scienze e Tecnologie Informatiche
    2008 - 2011
  • ITIS - Guglielmo Marconi
    Diploma perito informatico
    2005 - 2007

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