Alberto Celin
Hardware R&D at Microtec Innovating Wood- Claim this Profile
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Italiano Native or bilingual proficiency
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Inglese Full professional proficiency
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Spagnolo Elementary proficiency
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Tedesco Elementary proficiency
Topline Score
Bio
Credentials
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Italian - German Bilingualism Certificate, CEFR Level A2
Provincia Autonoma di BolzanoJun, 2021- Sep, 2024 -
Certificate in Advanced English - CEFR Level C1
Cambridge Assessment EnglishJan, 2019- Sep, 2024 -
SafeTTy Certified - Level 2
SafeTTy SystemsSep, 2016- Sep, 2024 -
ECDL
Liceo Scientifico Statale "P. Paleocapa" - RovigoJan, 2005- Sep, 2024
Experience
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Microtec Innovating Wood
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Italy
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Appliances, Electrical, and Electronics Manufacturing
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200 - 300 Employee
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Hardware R&D
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Oct 2019 - Present
Firmware development for cameras and embedded systems integrated in scanners for wood and food. Firmware development for cameras and embedded systems integrated in scanners for wood and food.
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Dialog Semiconductor
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United Kingdom
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Semiconductor Manufacturing
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500 - 600 Employee
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Verification Engineer
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Apr 2018 - Sep 2019
Digital design and verification of chips for audio and haptics applications in portable devices and wearables.
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Graduate Verification Engineer
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Dec 2016 - Mar 2018
Digital design and verification of chips for audio and haptics applications in portable devices and wearables.
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Dana Incorporated
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United States
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Motor Vehicle Manufacturing
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700 & Above Employee
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Electronics Engineer
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Sep 2015 - Nov 2016
R&D on embedded systems for off-highway vehicles. Design, configuration and integration of vehicular prototype systems. Firmware development. Rig and start-up of test benches for control units and drivelines. R&D on embedded systems for off-highway vehicles. Design, configuration and integration of vehicular prototype systems. Firmware development. Rig and start-up of test benches for control units and drivelines.
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Student Intern
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Jan 2015 - Jun 2015
The internship consisted in designing, synthetizing and simulating a testing framework for an asynchronous Network-on-Chip switch. It implied the creation of RTL models in Verilog and the development of an asynchronous design flow using Synopsys Design Compiler. The obtained post-synthesis model was simulated using ModelSim and the simulation was managed by an automated system, developed in Perl language, for the injection of stuck-at faults in the netlist under simulation. The internship consisted in designing, synthetizing and simulating a testing framework for an asynchronous Network-on-Chip switch. It implied the creation of RTL models in Verilog and the development of an asynchronous design flow using Synopsys Design Compiler. The obtained post-synthesis model was simulated using ModelSim and the simulation was managed by an automated system, developed in Perl language, for the injection of stuck-at faults in the netlist under simulation.
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Student Intern
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Apr 2011 - Jul 2011
The internship tasks included the modification of a design flow using Synopsys Design Compiler in order to add a scan-chain based testing framework to a switch for Network-on-Chip. TetraMAX ATPG was used to generate deterministic test patterns for the post-synthesis switch, RTL models were developed in Verilog and ModelSim was employed to simulate the system. The internship tasks included the modification of a design flow using Synopsys Design Compiler in order to add a scan-chain based testing framework to a switch for Network-on-Chip. TetraMAX ATPG was used to generate deterministic test patterns for the post-synthesis switch, RTL models were developed in Verilog and ModelSim was employed to simulate the system.
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Education
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2011 - 2015
Università degli Studi di Ferrara
MSc in Electronics and Telecommunications Engineering -
2007 - 2011
Università degli Studi di Ferrara
BSc in Electronics Engineering -
2002 - 2007
Liceo Scientifico Statale "P. Paleocapa" - Rovigo
High School Diploma
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