Experience

PULSAR Microelectronics

• Egypt
• Semiconductor Manufacturing
• 1 - 100 Employee

• Analog Design Engineer

  • Jul 2023 - Present

  Cairo, Egypt



Analog Devices

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• mmWave Graduation Project Student

  • Sep 2022 - Jul 2023

  Cairo, Egypt "PROGR0AMMABLE WIDEBAND MMWAVE TRANSCEIVER FRONT END COVERING MULTI-STANDARDS FROM 10 GHZ TO 50 GHZ IN TSMC65N". The project includes designing a Transmitter (Tx), Receiver (Rx) and a Phase-Locked Loop (PLL). The project is supervised by Dr. Mohamed El-Nozahi and Dr. Mostafa Gamal. The project is sponsored by Analog Devices Inc. (ADI). Final Discussion Grade: A+ BLOCKS CONTRIBUTION: • Designing a very challenging Ultra-Wideband Amplifier with Low Noise. Covering… Show more "PROGR0AMMABLE WIDEBAND MMWAVE TRANSCEIVER FRONT END COVERING MULTI-STANDARDS FROM 10 GHZ TO 50 GHZ IN TSMC65N". The project includes designing a Transmitter (Tx), Receiver (Rx) and a Phase-Locked Loop (PLL). The project is supervised by Dr. Mohamed El-Nozahi and Dr. Mostafa Gamal. The project is sponsored by Analog Devices Inc. (ADI). Final Discussion Grade: A+ BLOCKS CONTRIBUTION: • Designing a very challenging Ultra-Wideband Amplifier with Low Noise. Covering frequencies from 10 GHz to 50 GHz. Noise is critical since the block is 2nd stage of the Rx. It consists of 3 stages of inductively degenerated CS with inductive peaking and feedback per stage to extend bandwidth. Specs: NF=4dB, gain=18dB, max. ripple of 1dB and IIP3=-15dBm. • Designing a very challenging Programmable Image Rejection Band Pass Filter on which the whole receiver’s operation depends. It consists of cascaded Low pass and High pass filters (since wideband). Programmability is achieved by capacitive bank and linear designed switches. Specs: 30dB image rejection, Insertion loss=3dB, max. ripple of 1dB and IIP3=20dBm. • The Amplifier is inserted between the Low pass and High pass filters to avoid their interaction. • Full Layout of three blocks (including VDD) and EM simulation were performed using EMX. SYSTEM CONTRIBUTION: • Receiver System Design: Survey on Standards existing within frequency range from 10 GHz to 50 GHz, Rx Architecture Selection, Cascading analysis and Frequency bands planning. • Receiver Integration and verification. • PLL System: Frequency range (7 GHz to 14 GHz), Frequency multipliers values and Phase noise spec. • EMX process file was written. Show less



Faculty of Engineering, Ain Shams University

• Education Administration Programs
• 700 & Above Employee

• Student

  • Sep 2018 - Jul 2023

  Cairo, Egypt



Goodix Egypt

• Egypt
• Semiconductor Manufacturing
• 1 - 100 Employee

• RF/Analog IC Design Engineer Intern

  • Jul 2022 - Sep 2022

  Cairo, Egypt Full Design and Verification of Dual-Band IEEE 802.11a/g Wi-Fi Receiver.



Siemens EDA (Siemens Digital Industries Software)

• Software Development
• 700 & Above Employee

• Analog to Digital Converters Design and Verification

  • Feb 2022 - Feb 2022

  Cairo, Egypt Sampling& Quantization-SAR& Sigma delta ADCs– Switched cap circuits–DACs-testing and specs. Project: SAR ADC design and verification. (Training duration: 2 weeks - FEB 2022)



Siemens EDA (Siemens Digital Industries Software)

• Software Development
• 700 & Above Employee

• FPGA Digital Track Intern

  • Sep 2021 - Oct 2021

  Cairo, Egypt 7-day training in FPGA digital track at Siemens EDA (Mentor Graphics), taught by Dr. Ihab Adly. The content was: 1-Design and verification of combinational logic. 2-Design and verification of sequential logic. 3-FPGA implementation flow. 4-Timing closure on FPGA. 5-FSM design modeling. 6-FSM with datapath modeling. 7-Platform Designer: Building and programming a processor (NIOS II and ARM Cortex M0) on FPGA. Complete Design final TEAM project: Designing a… Show more 7-day training in FPGA digital track at Siemens EDA (Mentor Graphics), taught by Dr. Ihab Adly. The content was: 1-Design and verification of combinational logic. 2-Design and verification of sequential logic. 3-FPGA implementation flow. 4-Timing closure on FPGA. 5-FSM design modeling. 6-FSM with datapath modeling. 7-Platform Designer: Building and programming a processor (NIOS II and ARM Cortex M0) on FPGA. Complete Design final TEAM project: Designing a matrix multiplier circuit and implementing it in three different ways: FSMD (using Verilog), on NIOS II and on ARM Cortex M0. Functional, timing simulations and synthesis were done using Quartus and Modelsim softwares. Show less



Information Technology Institute (ITI)

• Egypt
• Professional Training and Coaching
• 700 & Above Employee

• Analog IC Design Intern

  • Aug 2021 - Sep 2021

  Egypt CMOS Analog IC Design The course was mainly in the design of CMOS Analog ICs which content was: • Single stage CMOS amplifiers (CS, CG& CD) design and analysis. • Telescopic and folded Cascodes design and analysis. • Frequency response. • Current mirrors with different topologies. • Differential amplifiers (Resistive and active loaded). • Five transistor OTA (5TOTA) and its stability, compensations and design. • gm/ID Design methodology with various design… Show more CMOS Analog IC Design The course was mainly in the design of CMOS Analog ICs which content was: • Single stage CMOS amplifiers (CS, CG& CD) design and analysis. • Telescopic and folded Cascodes design and analysis. • Frequency response. • Current mirrors with different topologies. • Differential amplifiers (Resistive and active loaded). • Five transistor OTA (5TOTA) and its stability, compensations and design. • gm/ID Design methodology with various design examples. • Negative feedback. • Noise. • OTA topologies. • Common mode feedback network CMFB. • Variability and mismatch. • Advanced biasing and references (band gap reference circuit). • Projects and labs. The training duration was 2 months (90 hours = 45 hours lectures + 45 hours labs + Quizzes). It contained 8 labs which were: 1) MOSFET long channel and short channel characteristics and basic simulations of RC circuit. 2) Common-source amplifier. 3) Cascode amplifier. 4) Frequency response of CD buffer. 5) Current mirrors. 6) Differential amplifier. 7) Negative feedback. 8) Noise simulation. Projects using Cadence Virtuoso and ADT which are: 1) OTA design. 2) Two-stage Miller OTA. 3) Fully differential folded Cascode OTA with CMFB network. 4) Final day design challenge: Designing a two-stage miller OTA with high bandwidth with no lab guidelines. Show less



Innovation Hub - IHub

• Egypt
• Education Administration Programs
• 1 - 100 Employee

• Summer Intern

  • Jul 2019 - Sep 2019

  Cairo, Egypt I was in a team of 7 students after my freshman year in Engineering ASU. We invented a remote-controlled car using Arduino, motors and wheels. It is controlled via a mobile application by using Bluetooth to connect it to mobile. We learned a lot and had a great experience such as teamwork and problem solving. We took the 4th place.