Experience

Synective Labs AB

• Sweden
• Software Development
• 1 - 100 Employee

• FPGA Consultant at Ericsson

  • Dec 2021 - Present

  Client: Ericsson S&T Department.Assignment: 6G Testbed / Zeus project.Tasks: - FPGA-to-FPGA high-speed communication. - Agilex board bring-up. - RTL (VHDL) development. - VUnit simulation.Keywords: Agilex, VHDL, VUnit, F-tile, HPS, Quartus, SignlaTap, Intel.

• FPGA Consultant at Automotive Customer

  • Sep 2021 - Dec 2021

  Client: Undisclosed Automotive Customer.Assignment: Data and Video logger based on Xilinx XCZU4 MPSoC.Tasks: - FPGA RTL (VHDL). - Arm CPU Software (C). - Integration of Xilinx and 3rd party IP for system monitoring, communication, and video (HDMI and eDP).Keywords: VHDL, C, Xilinx, ARM, HDMI, eDP.



Bitidentify Technology AB

• Stockholm, Sweden

• FPGA Engineer

  • Aug 2019 - Jun 2021

  Develop a special SATA port multiplier for data security. Keywords: Xilinx Vivado, kintex7, FPGA transceiver, ILA, Vunit, TCL, ddr3, MIG IP, SATA, high-speed communication, hard disk. Develop a special SATA port multiplier for data security. Keywords: Xilinx Vivado, kintex7, FPGA transceiver, ILA, Vunit, TCL, ddr3, MIG IP, SATA, high-speed communication, hard disk.



ESSIQ AB

• Sweden
• IT Services and IT Consulting
• 100 - 200 Employee

• Embedded FPGA Engineer

  • Jan 2019 - Jul 2019

  Embedded System and FPGA Consultant While waiting for an assignment, I invested my time in learning more about SystemVerilog and UVM, C programming, computer vision, machine learning, Linux Device Driver, YOCTO, Python, and mobile robotic and SLAM. Embedded System and FPGA Consultant While waiting for an assignment, I invested my time in learning more about SystemVerilog and UVM, C programming, computer vision, machine learning, Linux Device Driver, YOCTO, Python, and mobile robotic and SLAM.



BOMBARDIER

• Canada
• Aviation and Aerospace Component Manufacturing
• 700 & Above Employee

• FPGA Engineer (master thesis)

  • Feb 2018 - Jul 2018

  Master thesis project: High-speed communication scheme in OSI Layer 2 research and implementation in FPGA. My role was to develop, implement and test a high-speed communication link between FPGAs. Gained Skills: Xilinx ISE, ChipScope, Makefile, railway background, safety-critical system concepts, high-speed communication, and teamwork. Master thesis project: High-speed communication scheme in OSI Layer 2 research and implementation in FPGA. My role was to develop, implement and test a high-speed communication link between FPGAs. Gained Skills: Xilinx ISE, ChipScope, Makefile, railway background, safety-critical system concepts, high-speed communication, and teamwork.



KTH Royal Institute of Technology

• Sweden
• Higher Education
• 700 & Above Employee

• Lab Assistant

  • Nov 2017 - Dec 2017

  Lab assistant for Digital Design course. Lab assistant for Digital Design course.



Scania Group

• Sweden
• Motor Vehicle Manufacturing
• 700 & Above Employee

• LabView developer

  • Sep 2017 - Dec 2017

  Developing a Data Acquisition System on cRIO 9045 using LabView for Scania engine as a part of the Embedded Systems Project course at kth. Part of my work was involving planning and managing a sub-team. Gained Skills: LabView, rapid prototyping, sensors interfacing, trucks' engine background, management, and teamwork. Developing a Data Acquisition System on cRIO 9045 using LabView for Scania engine as a part of the Embedded Systems Project course at kth. Part of my work was involving planning and managing a sub-team. Gained Skills: LabView, rapid prototyping, sensors interfacing, trucks' engine background, management, and teamwork.



KTH Space Center

• Sweden
• Research Services
• 1 - 100 Employee

• VHDL programmer

  • Jan 2017 - Jul 2017

  Interfacing a low-cost CMOS camera to a Xilinx Zynq FPGA using VHDL in SUED experiment as a part of the kth MIST project. Gained Skills: Xilinx Vivado, logic analyzer, I2C, CMOS camera background, and meeting and reporting skills. Interfacing a low-cost CMOS camera to a Xilinx Zynq FPGA using VHDL in SUED experiment as a part of the kth MIST project. Gained Skills: Xilinx Vivado, logic analyzer, I2C, CMOS camera background, and meeting and reporting skills.



Yanzi Networks

• Sweden
• Software Development
• 1 - 100 Employee

• Assistant

  • Jun 2017 - Jun 2017

  My role was to assist and help preparing products for shipment and do various tasks in the warehouse. Also some matlab coding. My role was to assist and help preparing products for shipment and do various tasks in the warehouse. Also some matlab coding.



Leine Linde

• Sweden
• Appliances, Electrical, and Electronics Manufacturing
• 1 - 100 Employee

• Internship VHDL-Testbenche

  • Jan 2016 - Jul 2016

  Developing VHDL-testbenches for safety encoder firmware and performing simulations with Modelsim and relay and contactor switching test. Gained Skills: Swedish working environment and culture, structured-VHDL coding style, big project implementation, Modelsim, encoder background, and prototyping for testing. Developing VHDL-testbenches for safety encoder firmware and performing simulations with Modelsim and relay and contactor switching test. Gained Skills: Swedish working environment and culture, structured-VHDL coding style, big project implementation, Modelsim, encoder background, and prototyping for testing.