Aditi Singh

Graduate Teaching Assistant at College of Natural Sciences, The University of Texas at Austin
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Contact Information
us****@****om
(386) 825-5501
Location
Noida, Uttar Pradesh, India, IN
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Credentials

  • Build a Modern Computer from First Principles
    Hebrew University of Jerusalem - Hadassah
    Dec, 2020
    - Nov, 2024
  • Machine Learning
    Stanford Online
    Nov, 2020
    - Nov, 2024
  • Ordered Data Structures
    University of Illinois at Urbana-Champaign
    Oct, 2020
    - Nov, 2024
  • VLSI CAD Part 2 : Layout
    University of Illinois at Urbana-Champaign
    Aug, 2020
    - Nov, 2024
  • VLSI CAD Part I: Logic
    University of Illinois at Urbana-Champaign| Coursera
    Jul, 2020
    - Nov, 2024
  • Hardware Modelling using Verilog
    NPTEL
    Jan, 2019
    - Nov, 2024
  • Control of Mobile Robots
    Coursera
    Dec, 2017
    - Nov, 2024
  • IEEE Robotics Workshop, IIT Kharagpur
    IEEE
    Dec, 2016
    - Nov, 2024

Experience

  • College of Natural Sciences, The University of Texas at Austin
    • United States
    • Higher Education
    • 100 - 200 Employee
    • Graduate Teaching Assistant
      • Jan 2023 - Present

      Teaching assistant for the Integral Calculus for Science course under Prof. Laura Altuzar. Teaching assistant for the Integral Calculus for Science course under Prof. Laura Altuzar.

  • The University of Texas at Austin
    • United States
    • Higher Education
    • 700 & Above Employee
    • Student
      • Aug 2022 - Present

      VLSI 1:◦ 4 bit SRAM Custom Design - Schematic, Layout, Extraction : Custom designed a 4-bit 10 T SRAM, optimized for area, from schematic to custom layout design on Cadence Virtuoso. Performed and satisfied NC verilog logic test, prelayout simulation with Spectre, DRC and LVS with Calibre, and post layout simulation with HSPICE.◦ 16-bit ALU Design: Designed the schematic of a Kogge Stone Adder, Comparator, Barrel Shifter, and Decoder, optimized for minimum time operation. Performed STA on PrimeTime and achieved 0.732ns critical path delay for adder and post APR critical path delay of 2.42ns for the 16 bit ALU.◦ SSP Design and Integration: Designed, checked for functional correctness, and synthesized a Synchronous Serial Port (SSP) module in Verilog. Designed a bus controller, consisting of a master and slave module, conforming to the Wishbone Protocol and used it to integrate an ARM core module with instruction memory and the designed SSP. ◦ Implementation of AMBA AXI: Implemented and performed SVA based verification of AMBA AXI interconnect for 2 Masters 4 Slave configuration in Verilog.Computer Architecture:◦ LC3B microprocessor: Designed an LC-3b assembler in C to translate assembly language source code into the machine language (ISA) of LC-3b. Augmented the LC-3b micro-architecture to perform interrupt/exception handling and to support virtual memory. Also implemented a pipelined version of the microprocessor. Designed and tested an instruction level simulator and a cycle level micro-operations based simulator for the same.

  • Samsung Electronics
    • South Korea
    • Computers and Electronics Manufacturing
    • 700 & Above Employee
    • Engineer
      • Sep 2020 - Jul 2022

      • Samsung Internet Web Engine - Worked on the design and maintenance of the terrace layer of Sam-sung Internet, under the constraints of a sandboxed architecture utilizing concepts of multi-threading, job scheduling, and database optimization. Also contributed to the Chromium open source project.• New Feature Development - Developed the SFinder search feature using customized SQL queries and supporting engine level API's. Also developed the mass history add debug feature for testing purposes and pull to refresh feature for Samsung Internet.• Software Maintainability Index Enhancement - Helped to improve the cyclomatic complexity and duplicate code score of the terrace modules to 4.53 from 3.56. Also worked on unit test case writing for Java non UI files.• Patents - Part of the patents task force of Service R&D team. Actively worked on a multitude of patent ideas with fellow team members and IP team.

  • Indian Institute of Technology, Kharagpur
    • India
    • Higher Education
    • 700 & Above Employee
    • Student and Researcher
      • Sep 2016 - Jan 2022

      • Security verification with respect to timing leaks - under Prof. Dr Aritra Hazra - Implemented tool for verifying constant time hardware using timed automata concept. Developed timed automaton of the cache controller, RAM controller, and coherency manager on UPPAAL and designed UPPAL queries to check for timing leaks in these automatons.• Equivalence Checking of Combinational Netlists - under Prof. Dr Aritra Hazra - Developed a BDD based equivalence checker for circuits containing Don’t Care value (X) along with Boolean 0 and 1 values using the Colorado University Decision Diagram (CUDD) package for BDD manipulation. Verified for correct working on 12 combinational circuits from the LGSynth’91 benchmark suite.• Solar Assisted Battery Charger - under Prof. Dr Dibankar Debnath - Designed PCB of CUK DC-DC converter and feedback sensors for building an inhouse solar aided battery charger for E-Rickshaw application using OrCAD design software. Simplified tunable control scheme was also implemented for the charger and whole system was tested on hardware.• Comparator Performance Comparison - under Prof. Dr Asish Maity - Designed the schematic and layout of a Push Pull Output Comparator with/without Hysteresis band and Rail to Rail Comparator for given quiescent current and DC gain specification on Cadence.• MIPS RISC Pipelined Processor - under Prof. Dr Sreenivasa Rao - Designed a MIPS pipelined processor using the Icarus Verilog simulator, verified for correct operation on a Xilinx Spartan 3E FPGA Board.• Smart Toll Monitoring System - under Prof. Dr Debdoot Sheet -Built a working prototype of an XBEE/Zigbee based wireless communication system convoluted with RFID based car detection mechanism to monitor traffic at toll booths remotely.

  • Samsung Electronics
    • South Korea
    • Computers and Electronics Manufacturing
    • 700 & Above Employee
    • Summer Internship
      • May 2019 - Jul 2019

      • Constructed and implemented a Dynamic Beam Management algorithm for 5G New Radio (NR) to enable communication in the frequency band from 30GHz - 300GHz between the gNB and UE for the Initial Access Procedure and Beam Tracking. • Constructed and implemented a Dynamic Beam Management algorithm for 5G New Radio (NR) to enable communication in the frequency band from 30GHz - 300GHz between the gNB and UE for the Initial Access Procedure and Beam Tracking.

  • FlytBase
    • United States
    • Software Development
    • 1 - 100 Employee
    • Internship Trainee
      • May 2018 - Jul 2018

      • Designed a Modified PD based controller for drone path generation and traversal and tested for successful working on DJI Phantom Pro and DJI Matrice 100 hardware for simulated model of stationary and moving goose. • Designed a Modified PD based controller for drone path generation and traversal and tested for successful working on DJI Phantom Pro and DJI Matrice 100 hardware for simulated model of stationary and moving goose.

Education

  • The University of Texas at Austin
    Master of Science - MS, Electrical and Computer Engineering
    2022 - 2024
  • Indian Institute of Technology, Kharagpur
    Bachelor's degree, Electrical, Electronics and Communications Engineering
    2016 - 2020
  • Ryan International School, Navi Mumbai
    Science
    2014 - 2016
  • Delhi Public School - India
    2006 - 2016

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