Experience

Milandr

• Russian Federation
• Semiconductor Manufacturing
• 1 - 100 Employee

• Back-end Digital Designer

  • Jan 2020 - Present

  Backend designer of digital blocks with experience in RTL to GDS flow (Synthesis, Floorplanning, Power grid design, Place and Route, Clock tree synthesis, Static Timing Analysis, Signoff, IR Drop, Physical Verification (DRC/LVS)) using Cadence Innovus tools.

• Analog IC Layout Engineer

  • Aug 2018 - Dec 2019

  Physical layout design analog circuit blocks, such as inamp, iref, phy_lvds_out.



JSC MERI

• Analog IC Layout Engineer

  • Dec 2016 - Jul 2018

  Physical layout design of standard cell, analog circuits blocks including all back end checks for LVS, ERC and DRC using Cadence Virtuoso and Mentor Calibre tools. Physical layout design of standard cell, analog circuits blocks including all back end checks for LVS, ERC and DRC using Cadence Virtuoso and Mentor Calibre tools.