Adelina Khalirbaginova
Back-end Digital Designer at Milandr- Claim this Profile
Contact Information
us****@****om
(386) 825-5501
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Location
Moscow, Moscow City, Russia, RU
Languages
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Russian -
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English -
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Experience
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Milandr
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Russian Federation
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Semiconductor Manufacturing
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1 - 100 Employee
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Back-end Digital Designer
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Jan 2020 - Present
Backend designer of digital blocks with experience in RTL to GDS flow (Synthesis, Floorplanning, Power grid design, Place and Route, Clock tree synthesis, Static Timing Analysis, Signoff, IR Drop, Physical Verification (DRC/LVS)) using Cadence Innovus tools.
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Analog IC Layout Engineer
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Aug 2018 - Dec 2019
Physical layout design analog circuit blocks, such as inamp, iref, phy_lvds_out.
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Analog IC Layout Engineer
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Dec 2016 - Jul 2018
Physical layout design of standard cell, analog circuits blocks including all back end checks for LVS, ERC and DRC using Cadence Virtuoso and Mentor Calibre tools. Physical layout design of standard cell, analog circuits blocks including all back end checks for LVS, ERC and DRC using Cadence Virtuoso and Mentor Calibre tools.
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Education
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Московский Государственный Институт Электронной Техники (Технический Университет) (МИЭТ)
Bachelor's degree, Computer Science and Engineering
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