Application Engineer R&D TestLab at Advantest Europe GmbH

• May 2019 - Present

Advantest 93k Engineer

• May 2017 - May 2019

Deputed to client location - Advantest Gmbh (Germany) RDI programming and test time analysis using TP360 tool, test time breakdown Attended Digital User and AVI64 User Training Good understanding of legacy test program on Teradyne Flex, IG-XL tool and migration to 93K Device characterization across temperatures for multiple variants Worked on Correlation and Repeatability, Test Number mismatch between programs, STDF correlation Presently working in R&D compatibility test lab on different 93K ATEs

Semiconductor Test engineer/ Post Silicon Validation Engineer

• Nov 2013 - Apr 2017

• develop high quality and highly reliable test solutions, debug of all the functional, parametric , timing measurements tests and complete silicon validation• develop bench characterization HW and SW for IC analysis & debug the test program in a system environment • fully characterize silicon in an ATE and bench environment and communicate results• deliver a test solution that meets test cost goals• test program optimization involving yield enhancement and test time reduction, test program release and remote yield support.

DFT and ATE Test Development Engineer at Altera/Intel Sdn. Bhd. (client location)

• Mar 2016 - Mar 2017

Involved in DFT and Altera Test Systems (ATS) IC testing activities at customer site - Altera Corporation Sdn Bhd, Penang, Malaysia. RTL design and verification, Quartus development tool, hands-on experience in ATS tester