Experience

Astera Labs

• United States
• Semiconductor Manufacturing
• 100 - 200 Employee

• Senior Product Manager

  • Jan 2023 - Present

  Aries PCIe Smart Retimers

• Product Manager

  • Mar 2022 - Jan 2023

  Managed Industry’s first CXL product “Leo Smart Memory Controllers”



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Chief of Staff - Cloud & Enterprise Business Divison

  • Apr 2020 - Mar 2022

  • Strategic partner to VP/GM responsible for developing, managing, and evangelizing holistic business unit strategy• Managed Business Unit’s yearly Goals – Revenue, P&L, Product Margin, Long Range Plan• Managed technical and outbound marketing activities including developing keynotes, press releases, etc.• Drove requirements and definition for Silicon and IP products

• Business Development Manager

  • Jan 2021 - Feb 2022

  • Led business development for server security market segment • Drove low-end FPGA product definition in alignment with Intel Xeon Platforms roadmap

• Senior Field Application Engineer

  • May 2018 - Jul 2020

  • Delivered several design wins ($$M) for a diverse set of cloud and enterprise customers.• Trained customers in chip design, RTL code optimizations, schematic and layout • Specialized in PCIe based add in card products

• Applications Engineer

  • Apr 2017 - Apr 2018

  • Trained neural nets on GPUs and ran inference on FPGA, GPU and CPU to evaluate competitor’s AI inference solution• Resolved customer issues in the areas of timing Closure, RTL -Optimizations, Configuration and Flash Interface



University of Florida

• United States
• Higher Education
• 700 & Above Employee

• Graduate Research Assistant

  • May 2016 - Apr 2017

  • Explored applications to suit reconfigurable aspects of NOVO-G (FPGA based supercomputer) for National Science foundation project • Developed Lattice Boltzmann Kernel using VHDL and Verilog, data streaming through DMA interfacing • Explored applications to suit reconfigurable aspects of NOVO-G (FPGA based supercomputer) for National Science foundation project • Developed Lattice Boltzmann Kernel using VHDL and Verilog, data streaming through DMA interfacing