Experience

Ponos Technology
• Switzerland
• Computer Hardware Manufacturing
• 1 - 100 Employee
• Senior Hardware Design Engineer

  • Sep 2022 - Present


GTD

• Spain
• IT Services and IT Consulting
• 300 - 400 Employee

• FPGA Engineer

  • Nov 2019 - Aug 2022

  Architectural design and refinement of the FPGA firmware for the ITER nuclear fusion reactor via the F4E European agency. Acquire data from magnetic sensors in the FPGA and transmit them using 10 Gbps network interface (serial data to AXI stream, UDP). Real-time processing of the sensors data. Design, implementation and validation of IPs in Vivado Architectural design and refinement of the FPGA firmware for the ITER nuclear fusion reactor via the F4E European agency. Acquire data from magnetic sensors in the FPGA and transmit them using 10 Gbps network interface (serial data to AXI stream, UDP). Real-time processing of the sensors data. Design, implementation and validation of IPs in Vivado



Keysight Technologies

• United States
• Appliances, Electrical, and Electronics Manufacturing
• 700 & Above Employee

• R&D FPGA Engineer - Contractor

  • Jan 2019 - Oct 2019

  Architectural refinement and RTL development, simulation and implementation of new functionalities for FPGA-based products using VHDL and Vivado. Agile and Atlassian tools for project development: Jira, Confluence, Bitbucket Architectural refinement and RTL development, simulation and implementation of new functionalities for FPGA-based products using VHDL and Vivado. Agile and Atlassian tools for project development: Jira, Confluence, Bitbucket


Tesorion
• Netherlands
• Computer and Network Security
• 1 - 100 Employee
• FPGA Design Engineer at Tesorion

  • May 2018 - Dec 2018


Recore Systems

• Netherlands
• Semiconductors

• FPGA Design Engineer

  • Mar 2016 - Mar 2018

  At Recore Systems I worked in developing a fully custom system made up of multiple Xilinx FPGAs intended to high throughput real-time data analysis and feature extraction. The system required the design and implementation of custom IPs, develop of ad-hoc interconnects between different FPGAs, simulation and on-chip debugging. For the RTL coding I used VHDL and for the FPGA development, integration and testing I worked with diverse Xilinx tools: Vivado, Chipscope, xsdb, SDK. At Recore Systems I worked in developing a fully custom system made up of multiple Xilinx FPGAs intended to high throughput real-time data analysis and feature extraction. The system required the design and implementation of custom IPs, develop of ad-hoc interconnects between different FPGAs, simulation and on-chip debugging. For the RTL coding I used VHDL and for the FPGA development, integration and testing I worked with diverse Xilinx tools: Vivado, Chipscope, xsdb, SDK.


UAB - Universitat Autònoma de Barcelona
• R&D Engineer

  • Feb 2015 - Jan 2016

IMB-CNM, CSIC
• Spain
• Research Services
• 100 - 200 Employee
• Research and Development Engineer

  • Dec 2012 - Jul 2014