Experience

SRC Research Scholars Program

• United States
• Research Services
• 200 - 300 Employee

• Research Scholar

  • Feb 2023 - Present



Lockheed Martin

• United States
• Defense and Space Manufacturing
• 700 & Above Employee

• EEE Component Engineer

  • Feb 2018 - Present

  • Analyzed Solid State Device Military Specification Testing plans based on solid state physics and experimental statistics and determined each part’s lot electrical and mechanical suitability in space. • Collaborated with the U.S. Defense Logistics Agency’s Qualified Manufacturers (Kemet, Vishay, Microsemi, etc) to create hi-reliability custom parts suited to program’s needs and to solve EEE part anomalies and failures. • Cooperated with NASA and subcontractors during weekly EEE Parts… Show more • Analyzed Solid State Device Military Specification Testing plans based on solid state physics and experimental statistics and determined each part’s lot electrical and mechanical suitability in space. • Collaborated with the U.S. Defense Logistics Agency’s Qualified Manufacturers (Kemet, Vishay, Microsemi, etc) to create hi-reliability custom parts suited to program’s needs and to solve EEE part anomalies and failures. • Cooperated with NASA and subcontractors during weekly EEE Parts Control Board to analyze and to draft solutions using material knowledge and semiconductor device knowledge. • Facilitated new EEE part technology insertion process and analyzed parts’ electrical and mechanical suitability using semiconductor device physics for SiC MOSFET, NOR Flash, NAND Flash, and DDR2 SDRAM. • Initiated Orion EEE parts obsolescence management team effort to purchase EEE parts totaling more than $20 million Show less • Analyzed Solid State Device Military Specification Testing plans based on solid state physics and experimental statistics and determined each part’s lot electrical and mechanical suitability in space. • Collaborated with the U.S. Defense Logistics Agency’s Qualified Manufacturers (Kemet, Vishay, Microsemi, etc) to create hi-reliability custom parts suited to program’s needs and to solve EEE part anomalies and failures. • Cooperated with NASA and subcontractors during weekly EEE Parts… Show more • Analyzed Solid State Device Military Specification Testing plans based on solid state physics and experimental statistics and determined each part’s lot electrical and mechanical suitability in space. • Collaborated with the U.S. Defense Logistics Agency’s Qualified Manufacturers (Kemet, Vishay, Microsemi, etc) to create hi-reliability custom parts suited to program’s needs and to solve EEE part anomalies and failures. • Cooperated with NASA and subcontractors during weekly EEE Parts Control Board to analyze and to draft solutions using material knowledge and semiconductor device knowledge. • Facilitated new EEE part technology insertion process and analyzed parts’ electrical and mechanical suitability using semiconductor device physics for SiC MOSFET, NOR Flash, NAND Flash, and DDR2 SDRAM. • Initiated Orion EEE parts obsolescence management team effort to purchase EEE parts totaling more than $20 million Show less



Western Digital

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• Product Design Engineer - Memory Health

  • May 2022 - Aug 2022

  • 1 Trade Secret filed. • Further fine-tuned the WL-WL DC Stress Test with Dummy WLs using different voltage parameters for a 162-layer 3D NAND die to find the break condition and to reduce DPPM (Defective PPM) and Bad Blocks on the die. • Developed, performed, and analyzed the program to revert Vts on Dummy WLs that shifted during WL-WL DC Stress Test, also known as the Dummy Refresh program – WLR Test. • Drove the effort to develop Periphery Cycling Stress using new internal address… Show more • 1 Trade Secret filed. • Further fine-tuned the WL-WL DC Stress Test with Dummy WLs using different voltage parameters for a 162-layer 3D NAND die to find the break condition and to reduce DPPM (Defective PPM) and Bad Blocks on the die. • Developed, performed, and analyzed the program to revert Vts on Dummy WLs that shifted during WL-WL DC Stress Test, also known as the Dummy Refresh program – WLR Test. • Drove the effort to develop Periphery Cycling Stress using new internal address decoding techniques – WLR Test. • Initiated and spearheaded the effort to develop WL-LI IVR Screening Test to catch shorts between WL and LI. Show less • 1 Trade Secret filed. • Further fine-tuned the WL-WL DC Stress Test with Dummy WLs using different voltage parameters for a 162-layer 3D NAND die to find the break condition and to reduce DPPM (Defective PPM) and Bad Blocks on the die. • Developed, performed, and analyzed the program to revert Vts on Dummy WLs that shifted during WL-WL DC Stress Test, also known as the Dummy Refresh program – WLR Test. • Drove the effort to develop Periphery Cycling Stress using new internal address… Show more • 1 Trade Secret filed. • Further fine-tuned the WL-WL DC Stress Test with Dummy WLs using different voltage parameters for a 162-layer 3D NAND die to find the break condition and to reduce DPPM (Defective PPM) and Bad Blocks on the die. • Developed, performed, and analyzed the program to revert Vts on Dummy WLs that shifted during WL-WL DC Stress Test, also known as the Dummy Refresh program – WLR Test. • Drove the effort to develop Periphery Cycling Stress using new internal address decoding techniques – WLR Test. • Initiated and spearheaded the effort to develop WL-LI IVR Screening Test to catch shorts between WL and LI. Show less



Western Digital

• United States
• Computer Hardware Manufacturing
• 700 & Above Employee

• Product Design Engineer - Memoy Health

  • Jun 2021 - Sep 2021

  • Studied and examined 162-layer 3D NAND Flash structures and physics, which includes various failure modes and test modes of 3D NAND. • Studied and developed various screening and test scripts using a program called NanoLLT, which is based on C programming language. • Developed, performed, and analyzed Vt shift with WL-WL DC Stress Test using Dummy WLs using different Voltages, Block Zones, and Planes for a 162-layer 3D NAND die to find the break condition and to reduce DPPM (Defective… Show more • Studied and examined 162-layer 3D NAND Flash structures and physics, which includes various failure modes and test modes of 3D NAND. • Studied and developed various screening and test scripts using a program called NanoLLT, which is based on C programming language. • Developed, performed, and analyzed Vt shift with WL-WL DC Stress Test using Dummy WLs using different Voltages, Block Zones, and Planes for a 162-layer 3D NAND die to find the break condition and to reduce DPPM (Defective PPM) and Bad Blocks on the die. • Developed, performed, and analyzed the program to revert Vts on Dummy WLs that shifted during WL-WL DC Stress Test, also known as the Dummy Refresh program. • Formulated a global Wordline Zoning Document that summarizes all parameters, including WL border values, WL layer numbering, WL voltage parameters, and all default values. Show less • Studied and examined 162-layer 3D NAND Flash structures and physics, which includes various failure modes and test modes of 3D NAND. • Studied and developed various screening and test scripts using a program called NanoLLT, which is based on C programming language. • Developed, performed, and analyzed Vt shift with WL-WL DC Stress Test using Dummy WLs using different Voltages, Block Zones, and Planes for a 162-layer 3D NAND die to find the break condition and to reduce DPPM (Defective… Show more • Studied and examined 162-layer 3D NAND Flash structures and physics, which includes various failure modes and test modes of 3D NAND. • Studied and developed various screening and test scripts using a program called NanoLLT, which is based on C programming language. • Developed, performed, and analyzed Vt shift with WL-WL DC Stress Test using Dummy WLs using different Voltages, Block Zones, and Planes for a 162-layer 3D NAND die to find the break condition and to reduce DPPM (Defective PPM) and Bad Blocks on the die. • Developed, performed, and analyzed the program to revert Vts on Dummy WLs that shifted during WL-WL DC Stress Test, also known as the Dummy Refresh program. • Formulated a global Wordline Zoning Document that summarizes all parameters, including WL border values, WL layer numbering, WL voltage parameters, and all default values. Show less