Wenchao Liu

Vice President at Primarius Technologies
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Contact Information
us****@****om
(386) 825-5501
Location
Shanghai, China, CN
Languages
  • English -
  • Chinese -

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Experience

    • China
    • Semiconductor Manufacturing
    • 1 - 100 Employee
    • Vice President
      • Jan 2020 - Present

    • China
    • Semiconductors
    • 100 - 200 Employee
    • Technology Platform Director
      • Nov 2018 - Dec 2019

      Technology Platform responsibilities:- foundry process evaluation & comparison- process recommendation for product- IC design support and foundry interface- product tape out Technology Platform responsibilities:- foundry process evaluation & comparison- process recommendation for product- IC design support and foundry interface- product tape out

    • United States
    • Semiconductor Manufacturing
    • 700 & Above Employee
    • Senior Member of Technical Staff (Manager)
      • Feb 2009 - Nov 2018

      Team lead and project management: - Leading 40nm tech node device model development including test chip design, measurement, device and circuit performance analysis, model methodology. -Leading key customer support in 40nm technology device model library and design kit in different applications: Automotive, chip card and NVM Team lead and project management: - Leading 40nm tech node device model development including test chip design, measurement, device and circuit performance analysis, model methodology. -Leading key customer support in 40nm technology device model library and design kit in different applications: Automotive, chip card and NVM

    • United States
    • IT Services and IT Consulting
    • 700 & Above Employee
    • Research Partner in IBM (International Semiconductor Development Alliance)
      • Feb 2006 - Feb 2009

      - MOSFET stress effect modeling development, device characterization and passive model extraction for advance technology nodes- SPICE model methodology development from 65nm to 28nm tech nodes - MOSFET stress effect modeling development, device characterization and passive model extraction for advance technology nodes- SPICE model methodology development from 65nm to 28nm tech nodes

    • Semiconductors
    • 200 - 300 Employee
    • Senior Engineer
      • Aug 2005 - Feb 2006

      Device characterization and model/PDK development in 90nm node Device characterization and model/PDK development in 90nm node

    • China
    • Semiconductors
    • 1 - 100 Employee
    • Principal Engineer
      • Jul 2004 - Aug 2005

      Active and passive device characterization and SPICE model development in 0.13um tech node Active and passive device characterization and SPICE model development in 0.13um tech node

Education

  • Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Ph.D., Microelectronics
    2001 - 2004
  • Hunan University
    Master Degree, Materials Science
    1998 - 2001

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