Experience

Dolphin Design

• France
• Semiconductor Manufacturing
• 100 - 200 Employee

• Processing IPs & ASIC Product Line Manager

  • May 2020 - Present

• Digital Design Group Manager

  • Oct 2017 - May 2020

• Digital Design Group Technical Leader

  • Apr 2016 - Oct 2017

  Verification technical leader- In charge of all verification activities including IP/SOC verification, methodologies, reporting, continuous improvments, EDA licences management- Create the verification activity from scratch including verification flow, testbench infrastructure, reporting, CI (Jenkins)Low power technical leader- In charge of technical activity related to LP methodologies with UPF- SoC architecture- In charge of Qingshan demochip SoC architecture- Functional specification and power intent specificationPeople Management- Manage 4 people including annual evaluation, skills development plan... Show less



STMicroelectronics

• Switzerland
• Semiconductor Manufacturing
• 700 & Above Employee

• SoC design and verification engineer for Set-Top-Box products

  • Oct 2012 - Apr 2016

  SoC verification/design for Set-Top-Box STiH412, STiH312, STiH337 product family. Verification activities - Verification technical lead for STiH337 product - Test plan definition and implementation for many subsystems : GPU, graphic blitter, JPEG decoder, HDMI, Boot devices - Low-power verification (UPF-based) definition, platform updates and execution Design activities - GPU, graphic blitter integration at SoC level - Boot devices (NAND, SPI, eMMC) sub-systems integration at SoC level - RTL design for SoC infrastructure Power estimation activities - Create, develop and execute SoC infrastructure power estimation flow - Work closely with system architecture and implementation team - Extract power consumption, clock gating efficiency, power density for SoC IPs - SQL database for power figures management Infrastructure : - Tests development in C - Tests database management with GIT/Repo - Continuous integration using Jenkins - SoC SQL database development using Java Show less



ST-Ericsson

• Switzerland
• Semiconductor Manufacturing
• 500 - 600 Employee

• Graphic Processing Unit (GPU) verification team leader

  • Jan 2010 - Oct 2012

  Leading activities- Verification plan definition and execution with respect to SoC requirements for ST-Ericsson U85xx, U86xx, U96xx product families- Relationship with Imagination Technologies- Relationship with ST-Ericsson SoC teamMain activities- Integration of "Imagination (IMG)" IP (SGX544, Rogue) into ST-Ericsson GPU sub-sytem- Dedicated power management structure around IMG Rogue IP- RTL verification- GPU system C modeling for SoC teamPerformances characterization- Benchmarking- Memory latencies and core frequency variationLow Power (LP) verification- Dedicated verification plan- Advanced LP technics, multi-voltage verification- FDSOI technologyPower estimation- Same benchmarks as for performances characterization- Extract leakage and dynamic power consumption- Temperature and voltage scaling- Clock gating efficiency- Bulk and FDSOI librariesVerification methodologies / platform- SystemC/TLM based platform based- C-langage verification SW- Synopsys simulator for RTL and LP verification- Certitude- SQL database for verification results management (non regression status, coverage metrics, performances...) Show less

• Advanced design verification engineer

  • Jan 2008 - Dec 2010

  - H264 / MP4 / VC1 video encoder/decoder environment - VC1 codec sub-system verification - Power estimation methodology, simulations and reporting for all codecs - XTREME cadence co-emulation methodology - GATE level zero/back-annotated simulations before PG



STMicroelectronics

• Switzerland
• Semiconductor Manufacturing
• 700 & Above Employee

• Design Verification Engineer

  • Nov 2005 - 2007

  Video encoder/decoder IP verification - Variable-length-decoder block level verification - Build verification plan, platform & test implementation - Review with architects & designers - e/Specman verification environment - C language verification SW - Scripting Video encoder/decoder IP verification - Variable-length-decoder block level verification - Build verification plan, platform & test implementation - Review with architects & designers - e/Specman verification environment - C language verification SW - Scripting



PSI Electronics

• Semiconductors
• 1 - 100 Employee

• Design Verification Engineer

  • Apr 2005 - Nov 2005

  Subcontractor in ST-Microelectronics as SoC verification engineer on Nomadik project Subcontractor in ST-Microelectronics as SoC verification engineer on Nomadik project