Experience

Synkom Malaysia

• Malaysia
• Appliances, Electrical, and Electronics Manufacturing
• 1 - 100 Employee

• Design Engineer

  • Nov 2022 - Present

  - Responsible for the synthesis flow (process of translating RTL codes into synthesizable gate level netlist) by applying constraints to the design which also includes timing check. - Responsible for the formality check, spyglass as well as the netlist analysis check. - Responsible in flow automation such as STA and PV by generating tcsh script. - Responsible in generating ECO scripts. - Responsible for the synthesis flow (process of translating RTL codes into synthesizable gate level netlist) by applying constraints to the design which also includes timing check. - Responsible for the formality check, spyglass as well as the netlist analysis check. - Responsible in flow automation such as STA and PV by generating tcsh script. - Responsible in generating ECO scripts.



Symmid Corporation Sdn. Bhd.

• Malaysia
• Semiconductor Manufacturing
• 1 - 100 Employee

• Design Engineer

  • Nov 2021 - Present

  - A part of the consultation team for CREST internships - In charge of preparing training material for clients which involves STA ( Static Timing Analysis ) and physical verification using Cadence tool - A part of the consultation team for CREST internships - In charge of preparing training material for clients which involves STA ( Static Timing Analysis ) and physical verification using Cadence tool



Infinecs Systems Sdn. Bhd.

• Malaysia
• Semiconductor Manufacturing
• 1 - 100 Employee

• IC design engineer

  • Feb 2021 - Nov 2021

  - A part of the IP office team responsible to act as a collateral verification bridge between the IP and SOC - Responsible to meet the requirement set by the SOC team for integration purposes - Liaise with the IP team who provides the collateral for the IP office verification process - Perform verification process on the IP collateral and feedback on unexpected changes in collateral from IP team. - Carry out collateral generation to match the format that will be used by the SOC team. Show less



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• System-on-Chip Design Engineer

  • Aug 2019 - Jan 2021

  Structural Design Engineer - Working on Intellectual Property structural design blocks, delivering to the next generation SoC products - Knowledge in logic design flows and methodology from synthesis, place and route, ECO (engineering change order) to verification flow. - Experience in static timing analysis, clock tree synthesis - Experience in functional verification and reliability analysis Structural Design Engineer - Working on Intellectual Property structural design blocks, delivering to the next generation SoC products - Knowledge in logic design flows and methodology from synthesis, place and route, ECO (engineering change order) to verification flow. - Experience in static timing analysis, clock tree synthesis - Experience in functional verification and reliability analysis



Intel Corporation

• United States
• Semiconductor Manufacturing
• 700 & Above Employee

• Intern

  • Jun 2018 - Aug 2018

  -Scripting The task assigned is to write a script using Perl language to extract test name, tests start time and tests end time from the report text files, then arranged them in Microsoft Excel file. Meaning by executing this script, the specific test data can be extracted automatically into excel file, mannerly arranged. -Quality Check There are a lot of Design Rules Check, like minimum distance between the metals, polysilicon width to make sure the design can function properly. This process also has some stages that generate the data collateral required for structural design. For example, RTL (Register Transfer Level) code is converted to netlist by Design Compilation in this process, or so call synthesis. After this, UPF (Unified Power Format) and timing constraint file are also generated during this process. If the design violates the rules, the violations will be flagged. The intern’s task was to study the violations and find out the reason that they were flagged. Conclusions should be drawn if the violations could be waived and fix it if the violation cannot be waived. Show less