Akky Feimov
Senior FPGA engineer at QRate. Quantum Solutions- Claim this Profile
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English Professional working proficiency
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Russian Native or bilingual proficiency
Topline Score
Bio
Credentials
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Certificate of attendance "General English course, level Upper-intermediate / B2"
Your English Language School in DublinOct, 2022- Oct, 2024 -
Certificate after training "Zynq Ultrascale+ MPSoC for software developers"
TopTech AcademyDec, 2020- Oct, 2024 -
Certificate after training "Quantum Communication Methods"
National University of Science and Technology "MISIS"Dec, 2019- Oct, 2024
Experience
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QRate. Quantum Solutions
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Russian Federation
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Industrial Machinery Manufacturing
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1 - 100 Employee
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Senior FPGA engineer
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Apr 2019 - Present
I was involved in the development of a next-generation miniature device for quantum cryptography, which is based on a Xilinx Zynq MPSOC device with high-speed transceivers, lasers, PLLs, and DACs. My deal was cost-performance optimization of the system and improving the quality of used algorithms. We built several test generations and build and verify production prebuild. I have rebuilt and improved the architecture of legacy projects. Now they can work on more low frequency, compile 10 times faster, and extend 2 times less heat. We started to use SOPC developing process with IP cores, git, and confluence. Also, we started verification modules and integrations of modules. I was also consulting colleagues on different projects like QKD based on satellites and telescopes, quantum random generators, and the proof of concept projects of MDI QKD. I was a mentor to several new colleagues. Also, was solving the problem of receiving a signal from a satellite into fiber-optic-based detectors mounted on a telescope. Show less
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National University of Science and Technology "MISIS"
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1 - 100 Employee
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Senior FPGA engineer
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Oct 2020 - Present
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VNIIRT (All Rusian Institute of Radio Engineering)
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Moscow, Moscow City, Russia
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Senior FPGA engineer
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Apr 2011 - Mar 2019
Here I passed the path from intern to Senior FPGA Engineer. I used to develop HF receivers for modern phased-array-based radars. I made DSP cores, synchronization methods, and control logic on FPGA Altera ARRIA V and high-speed ADC based on the Jesd204B interface. I was involved in all steps of development from architectural decisions to building a testing environment in 5 radars. We learned and constantly improved our developing process. My parts of these were using Soft Core NIOSII for control FPGA project, using 1G/10G ethernet instead of legacy synchronous interfaces, using IP cores and integrations verification, and documenting for all developing modules. I offered an asynchronous model of control of all subsystems, and it was a really good idea. I developed the realization of several DSP algorithms like Fast matrix inversion based on QR dividing using systolic arrays, an algorithm of demodulation of radiolocation signal, an algorithm of stabilization noise floor on all receiving channels, an algorithm of calibration Phase Array based on Hadamard matrixes. I was a mentor of new colleagues and students, which had a diploma practice. Show less
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Education
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RTU MIREA
Engineer's degree, radio and electronics