Experience

Speedata.io

• Israel
• Semiconductors
• 1 - 100 Employee

• Senior VLSI Design Engineer

  • Mar 2022 - Present



Veriest

• Israel
• Semiconductor Manufacturing
• 100 - 200 Employee

• Senior Design Engineer

  • May 2020 - Feb 2022

  Contract for Western Digital, SVCI Width adapter project (narrow2wide, wide2narrow bridges and width adapter dma), GAT Delta Search and Release Engine, Host Write Release Engine, Host Interface Module top level integration

• Senior Design Engineer

  • Feb 2019 - May 2020

  Contractor on Western Digital, NVMe Host Emulator Project

• Design Verification Engineer

  • Sep 2018 - Feb 2019

  Contractor for Innoviz Technologies, Maui Project Module level verification (UVM), SVA implementation and debug

• Senior Design Engineer

  • Dec 2017 - Aug 2018

  Contractor on CEVA NeuPro Project Development of Memory SubSystem and memory access interconnect fabric

• Senior Design Engineer

  • Jun 2016 - Dec 2017

  Contractor on CEVA CNN ProjectDevelopment of CNN convolution core logic with In/Out data ordering, 520 MAC units and Activation. Project size ~10Mgates, 14nm@1.5GHz

• Senior Design Verification Engineer

  • Mar 2016 - Jun 2016

  IP Design Verification, Sandisk/Western Digital Moonshot Project Part of SD Moonshot verification team Verified Register access, HW/SW resets, interrupts and Profiling counters for HA, HABM, HAWA modules

• Senior Design Verification Engineer

  • May 2015 - Mar 2016

  VIP Development, Synopsys MHL Project Part of MHL VIP development team Development of MHL Source VIP for v2.2 and v3.2 protocols Development of TMDS link, Framer, TMDS Sequence Library, Exceptions and A/V Pattern generators

• Senior Design Engineer

  • Dec 2014 - May 2015

  IP Development, Veriest Internal Part of MIPI CSI2 v1.3 Transmitter IP development team Development of Application Layer (CPI) and Low Level Protocol Layer (D-Phy) submodules  Development of selfchecking Verilog testbench for IP pre-verification and IP delivery demonstration  The code is written in Verilog, RTL compiler is Synopsys VCS and linting check is done with Spyglass

• Senior Design Engineer

  • Sep 2014 - Dec 2014

  IP Development, Microsoft ALON Project Development of Register Indirect RAM Access Controller Task involved development of selfchecking Verilog testbench  The code is writen in Verilog, RTL compiler is Synopsys VCS and linting check is done with Spyglass

• Senior Design Engineer

  • Jul 2014 - Dec 2014

  SoC integration, Microsoft ALON Project Integration of DDR memory controller based on Synopsys IP cores and development of Memory Controller wrapper Task involved Synopsys IP generation tools coreConsultant and DesignWare DDR PHY Compiler The code is writen in Verilog, RTL compiler is Synopsys VCS and linting check is done with Spyglass



HDL Design House

• Serbia
• Semiconductor Manufacturing
• 200 - 300 Employee

• Senior Design Verification Engineer

  • Feb 2014 - Jul 2014

  RTL IP design on a IMM MCU project for Infineon Technologies, Austria

• Senior Design Verification Engineer

  • Dec 2013 - Feb 2014

  Top-Level verification of an Automotive MCU project for Spansion, GermanyFocus on DMA, SPI, CRC sub-systems



ELSYS Eastern Europe

• Serbia
• Semiconductor Manufacturing
• 100 - 200 Employee

• Senior Digital Design Engineer

  • Dec 2012 - Dec 2013

  Working as an ASIC design engineer on contract for Texas Instruments Germany as part of MSP digital IP team

• Senior Digital Design/Verification Engineer

  • Sep 2011 - Dec 2012

  Working as an ASIC design engineer on contract for Texas Instruments France as a part of OMAP6 IP team



Forma Ideale d.o.o

• Kragujevac

• Maintenance Manager

  • Jul 2007 - Sep 2011

  • Department/Project Management, tackling technical and organizational aspects of work in dynamic environment • Team Leadership – Interdisciplinary engineering team of 12 • Responsibility towards the 24/7, just-in-time / just-in-sequence production • Development of information system for tracking department activities • Development of new equipment, tools and auxiliary systems, process optimization • Department/Project Management, tackling technical and organizational aspects of work in dynamic environment • Team Leadership – Interdisciplinary engineering team of 12 • Responsibility towards the 24/7, just-in-time / just-in-sequence production • Development of information system for tracking department activities • Development of new equipment, tools and auxiliary systems, process optimization



Forma Ideale

• Kragujevac

• Maintenance Engineer

  • Mar 2007 - Jul 2007

  • Diagnostics of problems on CNC woodworking equipment (software and electronics), defining and executing corrective measures. • Analysis of equipment operation record and defining preventive measures • Overseeing and control of contractors on site • Diagnostics of problems on CNC woodworking equipment (software and electronics), defining and executing corrective measures. • Analysis of equipment operation record and defining preventive measures • Overseeing and control of contractors on site



HDL Design House

• Serbia
• Semiconductor Manufacturing
• 200 - 300 Employee

• ASIC Verification

  • Dec 2004 - Mar 2007

  • Working as an ASIC verification engineer on contract for Broadcom Israel Research, both remotely from Belgrade and in Tel Aviv• Development of Specman “e” Verification Environment for module and Sub-Chip level verification of 4 instances of multi-channel DMA servicing 4 RISC engines in a network interface controller• Documentation development: Test plan and Verification plan

• VHDL/Verilog behavioral modeling and verification

  • Aug 2002 - Mar 2007

  • Working on a contract for Free Model Foundry• VITAL modeling team technical management, training and QC• Documentation development• Development of VITAL and verilog behavioral models of AMD, Intel, Micron and IDT memory, processor and controller families. • Development of reusable VHDL testbench structure with general test description pseudo-language for model verification• HDL simulators : ModelSim, NCsim, VCS

• ASIC Design

  • Aug 2002 - Mar 2007

  • Working as an ASIC design engineer on contract for Texas Instruments France, both remotely from Belgrade and on-site.• Design and Maintenance of modules on several OMAP project: OMAP1710, OMAP2420, OMAP3420, N3G2• Individual module design and coordination other team members• Training preparation and organization on design flow training for other team members• Documentation development – high level functional specification, micro architecture and design specification, integration specification.• Synthesis tools : Synopsis Design Compiler, LEC, Fastscan Show less