Mithun Manjegawada
Digital Circuit Design Engineer at Dolphin Technology- Claim this Profile
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English -
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Kannada Native or bilingual proficiency
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hindi -
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Telugu -
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Bio
Haim Horovitz
I would like to take advantage of Linkedin to highlight Mithun's efforts during his summer internship at Xilinx. Mithun helped with developing schematics regression suite that was used for developing a new ERC tool - Mentor's PERC. He got familiar with PERC tool and created many schematics fail/pass test structures and ran the tool to debug them and bring them to a quality level that emulated real design circuits. In a short amount of time, Mithun got up to speed on all the electrical and ESD rules that we are using at Xilinx and how the tool checks them. He was very dedicated and worked with me to fine tune regression tests for the circuit requirements. He was very organized and created a good report of the whole project for a handover when he finished the job.
Haim Horovitz
I would like to take advantage of Linkedin to highlight Mithun's efforts during his summer internship at Xilinx. Mithun helped with developing schematics regression suite that was used for developing a new ERC tool - Mentor's PERC. He got familiar with PERC tool and created many schematics fail/pass test structures and ran the tool to debug them and bring them to a quality level that emulated real design circuits. In a short amount of time, Mithun got up to speed on all the electrical and ESD rules that we are using at Xilinx and how the tool checks them. He was very dedicated and worked with me to fine tune regression tests for the circuit requirements. He was very organized and created a good report of the whole project for a handover when he finished the job.
Haim Horovitz
I would like to take advantage of Linkedin to highlight Mithun's efforts during his summer internship at Xilinx. Mithun helped with developing schematics regression suite that was used for developing a new ERC tool - Mentor's PERC. He got familiar with PERC tool and created many schematics fail/pass test structures and ran the tool to debug them and bring them to a quality level that emulated real design circuits. In a short amount of time, Mithun got up to speed on all the electrical and ESD rules that we are using at Xilinx and how the tool checks them. He was very dedicated and worked with me to fine tune regression tests for the circuit requirements. He was very organized and created a good report of the whole project for a handover when he finished the job.
Haim Horovitz
I would like to take advantage of Linkedin to highlight Mithun's efforts during his summer internship at Xilinx. Mithun helped with developing schematics regression suite that was used for developing a new ERC tool - Mentor's PERC. He got familiar with PERC tool and created many schematics fail/pass test structures and ran the tool to debug them and bring them to a quality level that emulated real design circuits. In a short amount of time, Mithun got up to speed on all the electrical and ESD rules that we are using at Xilinx and how the tool checks them. He was very dedicated and worked with me to fine tune regression tests for the circuit requirements. He was very organized and created a good report of the whole project for a handover when he finished the job.
Experience
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Dolphin Technology
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United States
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Semiconductor Manufacturing
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1 - 100 Employee
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Digital Circuit Design Engineer
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Apr 2016 - Present
-Release and development of high speed I/O and standard cell products in 28nm, 16nm and higher technology nodes (TSMC & Global Foundry) -Running APR (Automatic Place &Route) (Cadence Encounter SoC), DRC and LVS checks for the I/O layouts generated through TCL commands on Encounter SoC. -Generating timing/power files, Verilog files using Compiler and liberty generator tools. -Running simulations, quality checks and characterization for I/O releases as per customer requirements. -Tools used: HSpice, Synopsys Finesim & Finewave, CADENCE Encounter or Innovus, L-Edit. Show less
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Nangate
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United States
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Semiconductor Manufacturing
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1 - 100 Employee
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Design Engineer
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Aug 2015 - Apr 2016
-Design of Standard cells at various technology nodes like 28nm, 130nm, 180nm using various foundries technology like TSMC, Global Foundries, UMC.-Member of core IP Design team, involved in layout design and optimization, physical design verification, DRM review and characterization.-RTL to GDSII using SoC Encounter tool for Automatic Place and Route of the standard cells designed, checking the port accessibility and quality of the cells.Designed cell architecture to provide Multi-Vt, Multi-channel length options. Show less
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EDA Intern
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Jan 2015 - Jul 2015
• Building a Standard Cell Library using TSMC 28nm HPM for 7tracks processes. It also includes Characterization and Optimization of Layouts.• Optimization of various complex combinational cell, Scan Flip-Flops and latches to reduce are and power consumption.• Design of Buffers, Multiplexers etc for with equal transition delays for CTS (Clock tree synthesis).• Created both 7 and 8 track low power high density library IP’s using both Global Foundaries and TSMC’s 28nm technolog y.• Designed cell architecture to provide multi-Vt, multi-channel length options. Migrated cells from TSMC’s HPM to HPC. Show less
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Xilinx
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United States
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Semiconductor Manufacturing
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700 & Above Employee
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FPGA integration and development intern
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Jun 2014 - Aug 2014
- IC design and Circuit Verification (ERC and ESD) for the 16nm technology FPGA device using Cadence VIRTUOSO. - Designed the schematics on virtuoso for all the electrical rules (ERC) that has to be followed in the new ultrascale 16nm FPGA device. - Performed Circuit Verification and ran PERC Test Regressions for the schematics designed, the Verification and Circuit Design involved ERC and ESD test cases for the device. - Involved in RTL design for the 20nm FPGA device, writing test benches for the behavioral models in Verilog and perform Formal Verification using LEC for Digital boundaries and ESP for Analog boundaries. - The tools used for Circuit Verification in the 16nm technology are CALIBRE RVE and CALIBRE PERC by Mentor graphics. Show less
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Education
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2013 - 2015
University of Southern California
Master of Science (MS), Electrical Engineering ( VLSI and Computer Architecture) -
2009 - 2013
Visvesvaraya Technological University
Bachelor's of Engineering, Electronics and Communications Engineering
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