Experience

Genesys Logic, Inc.

• Taiwan
• Semiconductors
• 1 - 100 Employee

• 技術經理

  • Nov 2021 - Present



Axiomtek

• Taiwan
• Computer Hardware Manufacturing
• 100 - 200 Employee

• Senior Engineer (資深工程師)

  • Dec 2018 - Sep 2021

  Embedded Core & Smart Engine Division Provided FPGA technical support cross Business Units, including performance improvement, consulting service, debug, training … etc. • Analyzed and optimized performance of SRAM access to meet timing requirement from customer. • Implemented Burst Mode for SRAM access, dramatically increase performance by 1500%. • Expand memory size of FPGA control card with PCI interface. • Provided FPGA Training and consulting. Embedded Core & Smart Engine Division Provided FPGA technical support cross Business Units, including performance improvement, consulting service, debug, training … etc. • Analyzed and optimized performance of SRAM access to meet timing requirement from customer. • Implemented Burst Mode for SRAM access, dramatically increase performance by 1500%. • Expand memory size of FPGA control card with PCI interface. • Provided FPGA Training and consulting.



GCC

• United States
• Industrial Machinery Manufacturing
• 1 - 100 Employee

• Senior Engineer (高級工程師)

  • Apr 2011 - Nov 2018

  Participated in the development of UV Inkjet Printer, UV Printer/Cutter and in charge of matters related to EE division including RTL coding, PCB design and test, cable arrangement, safety regulation … etc. • Implemented EtherCAT protocol with MII interface and using plastic optical fiber (POF) port to provide a low cost, high speed (100 Mbps) communication solution. • Implemented Xilinx Memory controller block (MCB) for FPGA to access DDR memory. Run functional simulation with Micron DDR Verilog model to verify data flow. Built a self-test function to scan whole DDR memory. Built a flow control module for MCB and integrated it with EtherCAT module to transceiver data. • Developed modules for board-to-board, chip- to-chip communication, such as UART, SPI, AIX BUS, and Maxim 1-Wire protocol. • Created a Xilinx ISE project targeted on Spartan series FPGA, defined control registers, integrated all submodules and built a Test bench to simulate the whole system. • Debugged with Xilinx ChipScope Pro to watch signals inside FPGA. • Designed testing procedure of main board I/O ports. • Architected, designed, verified POF coupler board and some other boards used on testing fixtures. • Supported Customer Service Division solving problems, developed new functions requested by end users. • Designed a BOM comparison tool in EXCEL. Highlight parts no longer provided or need to be noticed. Show things to do in a new work sheet with part number as its name. Efficiency improves by 5 times. Show less



Bridgeport Instruments LLC

• United States
• Appliances, Electrical, and Electronics Manufacturing
• 1 - 100 Employee

• Digital Circuit Design Engineer

  • Mar 2008 - Dec 2010

  Responsible for digital circuit design, RTL coding and simulation in Verilog. Worked together with a software engineer to develop the data acquisition board of the radiation detector, eMorpho and 4-channel qMorpho. • Upgraded system from an 8-bit to a 16-bit environment, integrated 3 Xilinx Spartan FPGAs into 1 Xilinx Virtex-4 and expanded radiation detectors support number from 1 to 4. • Implemented Xilinx FFT IP. Built a flow control module to generate address and necessary control signals. Wrote a test bench running functional simulation to verify data. • Accomplished several customized functions such as FFT data acquisition card, Dynamic delay module, Neutron counter and Hit pattern module. • Developed communication module between FPGA and Digi ConnectCoreTM 9P 9215 and SPI module to communicate with RTC, DAC, ADC and thermal sensor chips. • Implemented Xilinx Memory IP, such as Dual Port RAM, FIFO and ROM and developed a flow control module to generate address and control signals. Show less



國家中山科學研究院

• Taiwan
• Defense and Space Manufacturing
• 100 - 200 Employee

• Associate Engineer

  • Jan 2000 - Jul 2005

  Participated in UWB project, researched signal process architecture, implemented on a FPGA-based system with a MCU on it as well. • Developed scrambler, descrambler, encoder, decoder, BER modules in VHDL. • Built a golden pattern generator for each stage of the data flow. • Built a top level module for each transmitter and receiver side of UWB system and integrated all the submodules. • Built a test bench for a whole system. Run functional and post simulation with Modelsim to verify data flow. • Loaded transmission and receiver FPGA code into 2 individual boards. Boards are connected with flat cables instead of wireless signal. Tested with different transmission rate. Showed accumulated error number on 7-segment display. • Successfully passed functional simulation, post simulation and onboard testing. Transmission rate of onboard testing was 30 Mbps. Show less